Patents by Inventor Jose E. Moreira
Jose E. Moreira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200073668Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.Type: ApplicationFiled: November 7, 2019Publication date: March 5, 2020Inventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
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Patent number: 10545762Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.Type: GrantFiled: November 7, 2017Date of Patent: January 28, 2020Assignee: International Business Machines CorporationInventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
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Publication number: 20190018677Abstract: Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.Type: ApplicationFiled: July 11, 2017Publication date: January 17, 2019Inventors: GILES R. FRAZIER, HUNG Q. LE, JOSE E. MOREIRA, BRIAN W. THOMPTO
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Publication number: 20190018679Abstract: Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.Type: ApplicationFiled: October 27, 2017Publication date: January 17, 2019Inventors: GILES R. FRAZIER, HUNG Q. LE, JOSE E. MOREIRA, BRIAN W. THOMPTO
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Patent number: 9983878Abstract: Branch prediction is provided by generating a first index from a previous instruction address and from a first branch history vector having a first length. A second index is generated from the previous instruction address and from a second branch history vector that is longer than the first vector. Using the first index, a first branch prediction is retrieved from a first branch prediction table. Using the second index, a second branch prediction is retrieved from a second branch prediction table. Based upon additional branch history data, the first branch history vector and the second branch history vector are updated. A first hash value is generated from a current instruction address and the updated first branch history vector. A second hash value is generated from the current instruction address and the updated second branch history vector. One of the branch predictions are selected based upon the hash values.Type: GrantFiled: May 15, 2014Date of Patent: May 29, 2018Assignee: International Business Machines CorporationInventors: David S. Levitan, Jose E. Moreira, Mauricio J. Serrano
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Patent number: 9928158Abstract: A method for detecting a software-race condition in a program includes copying a state of a transaction of the program from a first core of a multi-core processor to at least one additional core of the multi-core processor, running the transaction, redundantly, on the first core and the at least one additional core given the state, outputting a result of the first core and the at least one additional core, and detecting a difference in the results between the first core and the at least one additional core, wherein the difference indicates the software-race condition.Type: GrantFiled: January 30, 2016Date of Patent: March 27, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold W. Cain, III, David M. Daly, Michael C. Huang, Kattamuri Ekanadham, Jose E. Moreira, Mauricio J. Serrano
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Publication number: 20180067746Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.Type: ApplicationFiled: November 7, 2017Publication date: March 8, 2018Inventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
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Patent number: 9910781Abstract: Embodiments relate to a page table including a data fetch width indicator. An aspect includes allocating a memory page in a main memory to an application. Another aspect includes creating a page table entry corresponding to the memory page in the page table. Another aspect includes determining, by a data fetch width indicator determination logic, the data fetch width indicator for the memory page. Another aspect includes sending a notification of the data fetch width indicator from the data fetch width indicator determination logic to supervisory software. Another aspect includes setting the data fetch width indicator in the page table entry by the supervisory software based on the notification. Another aspect includes, based on a cache miss in the cache memory corresponding to an address that is located in the memory page, fetching an amount of data from the memory page based on the data fetch width indicator.Type: GrantFiled: December 19, 2016Date of Patent: March 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael K. Gschwind, Jose E. Moreira, Balaram Sinharoy
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Patent number: 9904551Abstract: Branch prediction is provided by generating a first index from a previous instruction address and from a first branch history vector having a first length. A second index is generated from the previous instruction address and from a second branch history vector that is longer than the first vector. Using the first index, a first branch prediction is retrieved from a first branch prediction table. Using the second index, a second branch prediction is retrieved from a second branch prediction table. Based upon additional branch history data, the first branch history vector and the second branch history vector are updated. A first hash value is generated from a current instruction address and the updated first branch history vector. A second hash value is generated from the current instruction address and the updated second branch history vector. One of the branch predictions are selected based upon the hash values.Type: GrantFiled: November 3, 2016Date of Patent: February 27, 2018Assignee: International Business Machines CorporationInventors: David S. Levitan, Jose E. Moreira, Mauricio J. Serrano
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Patent number: 9898295Abstract: Branch prediction is provided by generating a first index from a previous instruction address and from a first branch history vector having a first length. A second index is generated from the previous instruction address and from a second branch history vector that is longer than the first vector. Using the first index, a first branch prediction is retrieved from a first branch prediction table. Using the second index, a second branch prediction is retrieved from a second branch prediction table. Based upon additional branch history data, the first branch history vector and the second branch history vector are updated. A first hash value is generated from a current instruction address and the updated first branch history vector. A second hash value is generated from the current instruction address and the updated second branch history vector. One of the branch predictions are selected based upon the hash values.Type: GrantFiled: November 3, 2016Date of Patent: February 20, 2018Assignee: International Business Machines CorporationInventors: David S. Levitan, Jose E. Moreira, Mauricio J. Serrano
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Patent number: 9870229Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.Type: GrantFiled: September 29, 2015Date of Patent: January 16, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
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Patent number: 9804879Abstract: Performing server virtual machine image migration and dependent server virtual machine image discovery in parallel is provided. Migration of a server virtual machine image that performs a workload is started to a client device via a network and, in parallel, an identity is continuously discovered of a set of dependent server virtual machine images corresponding to the server virtual machine image being migrated to the client device. In response to discovering the identity of the set of dependent server virtual machine images, a server migration pattern of the discovered set of dependent server virtual machine images is generated for the workload. A level of risk corresponding to migrating each dependent server virtual machine image of the discovered set of dependent server virtual machine images to the client device is calculated based on the server migration pattern of the discovered set of dependent server virtual machine images for the workload.Type: GrantFiled: May 14, 2015Date of Patent: October 31, 2017Assignee: International Business Machines CorporationInventors: Nikolaos Anerousis, Kun Bai, Hubertus Franke, Jinho Hwang, Jose E. Moreira, Maja Vukovic
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Patent number: 9785461Abstract: Performing server virtual machine image migration and dependent server virtual machine image discovery in parallel is provided. Migration of a server virtual machine image that performs a workload is started to a client device via a network and, in parallel, an identity is continuously discovered of a set of dependent server virtual machine images corresponding to the server virtual machine image being migrated to the client device. In response to discovering the identity of the set of dependent server virtual machine images, a server migration pattern of the discovered set of dependent server virtual machine images is generated for the workload. A level of risk corresponding to migrating each dependent server virtual machine image of the discovered set of dependent server virtual machine images to the client device is calculated based on the server migration pattern of the discovered set of dependent server virtual machine images for the workload.Type: GrantFiled: June 19, 2015Date of Patent: October 10, 2017Assignee: International Business Machines CorporationInventors: Nikolaos Anerousis, Kun Bai, Hubertus Franke, Jinho Hwang, Jose E. Moreira, Maja Vukovic
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Patent number: 9760133Abstract: There is provided an apparatus, a method and computer program product for managing one or more components of an electronic machine. A user connects one or more components to an electronic machine in parallel. The electronic machine determines whether the components are failed. A latch device, attached to each component, automatically locks one or more of the components to the electronic machine if the one or more of the components are not failed. The electromechanical latch automatically releases the one or more of the components from the electronic machine if the one or more of the components are failed.Type: GrantFiled: May 23, 2014Date of Patent: September 12, 2017Assignee: International Business Machines CorporationInventors: Harold W. Cain, III, David M. Daly, Jose E. Moreira
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Patent number: 9720696Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.Type: GrantFiled: September 30, 2014Date of Patent: August 1, 2017Assignee: International Business Machines CorporationInventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
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Patent number: 9626187Abstract: Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.Type: GrantFiled: May 27, 2010Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventors: Harold W. Cain, III, Bradly G. Frey, Benjamin Herrenschmidt, Hung Q. Le, Cathy May, Maged M. Michael, Jose E. Moreira, Priya A. Nagpurkar, Naresh Nayar, Randal C. Swanberg
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Patent number: 9619356Abstract: A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, periodically synchronizing the transaction on the cores throughout execution of the transaction, comparing results of the transaction on the cores, and determining an error in one or more of the cores.Type: GrantFiled: December 9, 2015Date of Patent: April 11, 2017Assignee: International Business Machines CorporationInventors: Harold W. Cain, III, David M. Daly, Kattamuri Ekanadham, Michael C. Huang, Jose E. Moreira, Mauricio J. Serrano
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Publication number: 20170097892Abstract: Embodiments relate to a page table including a data fetch width indicator. An aspect includes allocating a memory page in a main memory to an application. Another aspect includes creating a page table entry corresponding to the memory page in the page table. Another aspect includes determining, by a data fetch width indicator determination logic, the data fetch width indicator for the memory page. Another aspect includes sending a notification of the data fetch width indicator from the data fetch width indicator determination logic to supervisory software. Another aspect includes setting the data fetch width indicator in the page table entry by the supervisory software based on the notification. Another aspect includes, based on a cache miss in the cache memory corresponding to an address that is located in the memory page, fetching an amount of data from the memory page based on the data fetch width indicator.Type: ApplicationFiled: December 19, 2016Publication date: April 6, 2017Inventors: Michael K. Gschwind, Jose E. Moreira, Balaram Sinharoy
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Patent number: 9582423Abstract: Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to a first application that is executed by a processor of a computer. Another aspect includes maintaining, by the counter, a count of a number of times adjacent cache lines in the cache memory that correspond to the first memory region are touched by the processor. Another aspect includes determining an update to a data fetch width indicator corresponding to the first memory region based on the counter. Another aspect includes sending a hardware notification from a counter management module to supervisory software of the computer of the update to the data fetch width indicator. Yet another aspect includes updating, by the supervisory software, the data fetch width indicator of the first memory region in the main memory based on the hardware notification.Type: GrantFiled: June 20, 2016Date of Patent: February 28, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael K. Gschwind, Jose E. Moreira
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Patent number: 9582424Abstract: Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to a first application that is executed by a processor of a computer. Another aspect includes maintaining, by the counter, a count of a number of times adjacent cache lines in the cache memory that correspond to the first memory region are touched by the processor. Another aspect includes determining an update to a data fetch width indicator corresponding to the first memory region based on the counter. Another aspect includes sending a hardware notification from a counter management module to supervisory software of the computer of the update to the data fetch width indicator. Yet another aspect includes updating, by the supervisory software, the data fetch width indicator of the first memory region in the main memory based on the hardware notification.Type: GrantFiled: June 20, 2016Date of Patent: February 28, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael K. Gschwind, Jose E. Moreira