Patents by Inventor Jose Joseph
Jose Joseph has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110278570Abstract: Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.Type: ApplicationFiled: August 1, 2011Publication date: November 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alvin Jose Joseph, Ramana Murty Malladi, James Albert Slinkman
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Patent number: 8035198Abstract: A through wafer via structure. The structure includes: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to between greater than halfway to and all the way to the bottom surface of the substrate. Also methods for fabricating the though wafer via structure.Type: GrantFiled: August 8, 2008Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Hanyi Ding, Alvin Jose Joseph, Anthony Kendall Stamper
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Patent number: 8020128Abstract: Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.Type: GrantFiled: June 29, 2009Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Alvin Jose Joseph, Ramana Murty Malladi, James Albert Slinkman
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Publication number: 20110018060Abstract: Methods and structures for improving substrate loss and linearity in SOI substrates. The methods include forming damaged crystal structure regions under the buried oxide layer of SOI substrates and the structures included damaged crystal structure regions under the buried oxide layer of the SOI substrate.Type: ApplicationFiled: July 22, 2009Publication date: January 27, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alan Bernard Botula, David S. Collins, Alvin Jose Joseph, Howard Smith Landis, James Albert Slinkman, Anthony K. Stamper
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Publication number: 20100327280Abstract: Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.Type: ApplicationFiled: June 29, 2009Publication date: December 30, 2010Applicant: International Business Machines CorporationInventors: Alvin Jose Joseph, Ramana Murty Malladi, James Albert Slinkman
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Patent number: 7851923Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.Type: GrantFiled: March 25, 2009Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Mete Erturk, Robert A. Groves, Jeffrey Bowman Johnson, Alvin Jose Joseph, Qizhi Liu, Edmund Juris Sprogis, Anthony Kendall Stamper
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Patent number: 7844901Abstract: Methods and apparatus provide for a self-enclosed timeline trimmer to create a circular timeline placed over a video that graphically represents the entire duration of a video. Specifically, the self-enclosed timeline trimmer receives a video. The self-enclosed timeline trimmer generates a self-enclosed timeline to represent a duration of the video incremented according to a first unit of time. The self-enclosed timeline is layered over at least a portion of the video. The self-enclosed timeline trimmer represents a start of the video on the self-enclosed timeline and an end of the video on the self-enclosed timeline. The self-enclosed timeline trimmer displays the duration of the video in its entirety by connecting the start and the end of the video on the self-enclosed timeline. Further, the self-enclosed timeline trimmer is well suited for video editing on mobile computer devices, wireless computer devices, and for portable computer devices.Type: GrantFiled: March 20, 2007Date of Patent: November 30, 2010Assignee: Adobe Systems IncorporatedInventor: Jose Joseph
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Publication number: 20100230752Abstract: A structure, and a method for forming the same. The structure includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, N active semiconductor regions on the buried dielectric layer, N active devices on the N active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, a protection layer on the N active devices and the N active semiconductor regions, but not on the plurality of dummy regions. The N active devices comprise first active regions which comprise a first material. The plurality of dummy regions comprise first dummy regions which comprise the first material. A first pattern density of the first active regions and the first dummy regions is uniform across the structure. A trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions.Type: ApplicationFiled: August 26, 2009Publication date: September 16, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alan Bernard Botula, David S. Collins, Alvin Jose Joseph, Howard Smith Landis, James Albert Slinkman
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Patent number: 7772083Abstract: An electrical structure and method of forming. The method includes providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over the semiconductor substrate, and a silicon on insulator layer (SOI) formed over and in contact with the BOX layer. The SOI layer comprises shallow trench isolation (STI) structures formed between electrical devices. A first photoresist layer is formed over the STI structures and the electrical devices. Portions of said first photoresist layer, portions of the STI structures, and portions of the BOX layer are removed resulting in formed trenches. Ion implants are formed within portions of the semiconductor substrate. Remaining portions of the first photoresist layer are removed. A dielectric layer is formed over the electrical devices and within the trenches. A second photoresist layer is formed over the dielectric layer. Portions of the second photoresist layer are removed.Type: GrantFiled: December 29, 2008Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventors: Alan Bernard Botula, Michael Lawrence Gautsch, Alvin Jose Joseph, Max Gerald Levy, James Albert Slinkman
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Patent number: 7759789Abstract: A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled vias are contacted with a thermoelectric cooler to remove excess heat from the semiconductor device or devices.Type: GrantFiled: January 14, 2008Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Kai Di Feng, Alvin Jose Joseph, Donald J. Papae, Xiaojin Wei
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Publication number: 20100164075Abstract: An electrical structure and method of forming. The method includes providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over the semiconductor substrate, and a silicon on insulator layer (SOI) formed over and in contact with the BOX layer. The SOI layer comprises shallow trench isolation (STI) structures formed between electrical devices. A first photoresist layer is formed over the STI structures and the electrical devices. Portions of said first photoresist layer, portions of the STI structures, and portions of the BOX layer are removed resulting in formed trenches. Ion implants are formed within portions of the semiconductor substrate. Remaining portions of the first photoresist layer are removed. A dielectric layer is formed over the electrical devices and within the trenches. A second photoresist layer is formed over the dielectric layer. Portions of the second photoresist layer are removed.Type: ApplicationFiled: December 29, 2008Publication date: July 1, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alan Bernard Botula, Michael Lawrence Gautsch, Alvin Jose Joseph, Max Gerald Levy, James Albert Slinkman
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Publication number: 20100032808Abstract: A through wafer via structure. The structure includes: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to between greater than halfway to and all the way to the bottom surface of the substrate. Also methods for fabricating the though wafer via structure.Type: ApplicationFiled: August 8, 2008Publication date: February 11, 2010Inventors: Hanyi Ding, Alvin Jose Joseph, Anthony Kendall Stamper
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Publication number: 20100032810Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.Type: ApplicationFiled: August 8, 2008Publication date: February 11, 2010Inventors: Hanyi Ding, Alvin Jose Joseph, Anthony Kendall Stamper
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Publication number: 20100032811Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate.Type: ApplicationFiled: August 8, 2008Publication date: February 11, 2010Inventors: Hanyi Ding, Alvin Jose Joseph, Anthony Kendall Stamper
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Publication number: 20090184423Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.Type: ApplicationFiled: March 25, 2009Publication date: July 23, 2009Inventors: Mete Erturk, Robert A. Groves, Jeffrey Bowman Johnson, Alvin Jose Joseph, Qizhi Liu, Edmund Juris Sprogis, Anthony Kendall Stamper
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Patent number: 7563714Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter Of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.Type: GrantFiled: January 13, 2006Date of Patent: July 21, 2009Assignee: International Business Machines CorporationInventors: Mete Erturk, Robert A. Groves, Jeffrey Bowman Johnson, Alvin Jose Joseph, Qizhi Liu, Edmund Juris Sprogis, Anthony Kendall Stamper
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Publication number: 20090179323Abstract: A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled vias are contacted with a thermoelectric cooler to remove excess heat from the semiconductor device or devices.Type: ApplicationFiled: January 14, 2008Publication date: July 16, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai Di Feng, Alvin Jose Joseph, Donald J. Papae, Xiaojin Wei
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Patent number: 7521327Abstract: A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.Type: GrantFiled: March 17, 2006Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Alvin Jose Joseph, Qizhi Liu
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Publication number: 20060133957Abstract: A device and method for use with a centrifuge for fragmenting solute or particulate material contained in a liquid sample are disclosed. The device includes a substrate adapted to be supported within a centrifuge tube, and providing a microchannel defining a plurality of shear regions. Material contained in a liquid sample applied to the device, with such supported in a centrifuge tube within a centrifuge, is fragmented by shearing as the sample is forced successively through the plurality of shear regions in the microchannel, when the selected centrifugal force applied to the tube.Type: ApplicationFiled: January 16, 2004Publication date: June 22, 2006Inventors: Merrill Knapp, Victor Aguero, Jose Joseph, Keith Laderoute, Richard Heydt, Rachel McCloskey
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Patent number: 7038298Abstract: A high fT and fmax bipolar transistor (100) includes an emitter (104), a base (120), and a collector (116). The emitter has a lower portion (108) and an upper portion (112) that extends beyond the lower portion. The base includes an intrinsic base (14) and an extrinsic base (144). The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor (148) that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor (152) that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.Type: GrantFiled: June 24, 2003Date of Patent: May 2, 2006Assignee: International Business Machines CorporationInventors: Alvin Jose Joseph, Qizhi Liu