Abstract: A system and method for multi-level context switching in an electronic network comprises a control state machine configured to implement a data priority scheme, a return address generator configured to hold and release return addresses for interrupted instruction modules in accordance with the data priority scheme and context information from the electronic network, and a processor configured to process data from the electronic network in accordance with the data priority scheme and the context information. Receive registers stores data received from the electronic network. The control state machine includes a switch address generator and a program counter select. The switch address generator outputs a switch address, which is an address for a first instruction for a selected-context instruction module. The return address generator holds and releases the return addresses, which are addresses of next consecutive instructions, when an instruction module is interrupted for a context switch.

Abstract: A system and method for context switching in an electronic network comprises a memory configured to store instruction modules, each instruction module corresponding to a context, a processor that executes the instruction modules, and a control state machine. The control state machine selects one of the instruction modules for execution by the processor according to context information from the electronic network. The control state machine includes a switch address generator, a return address register, and a program counter select. The switch address generator outputs a switch address, which is an address for a first instruction for a selected-context instruction module. The return address register stores a return address, which is an address of a next consecutive instruction, when an instruction module is interrupted for a context switch.

Abstract: A method of and apparatus for providing clock signals for synchronizing operation of elements of a digital interface system between an IEEE 1394 serial bus and a personal computer interface (PCI) bus. The digital interface system includes a number of functional elements in addition to a PCI interface element. Each of the functional elements and the PCI interface element receives a system clock signal via a clock tree. The clock tree derives individual clock signals from the system clock and provides these individual clock signals to each of the functional elements. The clock tree is balanced such that each clock transition occurs at each of the functional elements, other than the PCI interface element, at substantially the same time. Clock balancing is achieved through appropriate circuit layout and insertion of delay elements. The clock tree also derives a clock signal for the PCI interface element from the system clock signal.

Abstract: A system and method for multi-level context switching in an electronic network comprises a control state machine configured to implement a data priority scheme, a return address generator configured to hold and release return addresses for interrupted instruction modules in accordance with the data priority scheme and context information from the electronic network, and a processor configured to process data from the electronic network in accordance with the data priority scheme and the context information. Receive registers stores data received from the electronic network. The control state machine includes a switch address generator and a program counter select. The switch address generator outputs a switch address, which is an address for a first instruction for a selected-context instruction module. The return address generator holds and releases the return addresses, which are addresses of next consecutive instructions, when an instruction module is interrupted for a context switch.