Patents by Inventor Jose L. Neves
Jose L. Neves has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10169526Abstract: An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.Type: GrantFiled: November 14, 2017Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kerim Kalafala, Tsz-Mei Ko, Ravichander Ledalla, Alice H. Lee, Adam P. Matheny, Jose L. Neves, Gregory M. Schaeffer
-
Patent number: 9934341Abstract: A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.Type: GrantFiled: November 11, 2015Date of Patent: April 3, 2018Assignee: International Business Machines CorporationInventors: Christopher J. Berry, Chris A. Cavitt, Adam P. Matheny, Jose L. Neves, Jesse P. Surprise, Michael H. Wood
-
Patent number: 9928322Abstract: A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.Type: GrantFiled: April 22, 2016Date of Patent: March 27, 2018Assignee: International Business Machines CorporationInventors: Christopher J. Berry, Chris A. Cavitt, Adam P. Matheny, Jose L. Neves, Jesse P. Surprise, Michael H. Wood
-
Publication number: 20180068052Abstract: An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.Type: ApplicationFiled: November 14, 2017Publication date: March 8, 2018Inventors: Kerim Kalafala, Tsz-Mei Ko, Ravichander Ledalla, Alice H. Lee, Adam P. Matheny, Jose L. Neves, Gregory M. Schaeffer
-
Patent number: 9858383Abstract: An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.Type: GrantFiled: December 18, 2015Date of Patent: January 2, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kerim Kalafala, Tsz-Mei Ko, Ravichander Ledalla, Alice H. Lee, Adam P. Matheny, Jose L. Neves, Gregory M. Schaeffer
-
Patent number: 9734270Abstract: Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.Type: GrantFiled: September 1, 2015Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Berry, Kaustav Guha, Jose L. Neves, Haifeng Qian, Sourav Saha
-
Patent number: 9703910Abstract: Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.Type: GrantFiled: July 9, 2015Date of Patent: July 11, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Berry, Kaustav Guha, Jose L. Neves, Haifeng Qian, Sourav Saha
-
Publication number: 20170177784Abstract: An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.Type: ApplicationFiled: December 18, 2015Publication date: June 22, 2017Inventors: Kerim Kalafala, Tsz-Mei Ko, Ravichander Ledalla, Alice H. Lee, Adam P. Matheny, Jose L. Neves, Gregory M. Schaeffer
-
Publication number: 20170132341Abstract: A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.Type: ApplicationFiled: April 22, 2016Publication date: May 11, 2017Inventors: Christopher J. Berry, Chris A. Cavitt, Adam P. Matheny, Jose L. Neves, Jesse P. Surprise, Michael H. Wood
-
Publication number: 20170132340Abstract: A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.Type: ApplicationFiled: November 11, 2015Publication date: May 11, 2017Inventors: Christopher J. Berry, Chris A. Cavitt, Adam P. Matheny, Jose L. Neves, Jesse P. Surprise, Michael H. Wood
-
Publication number: 20170011156Abstract: Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.Type: ApplicationFiled: July 9, 2015Publication date: January 12, 2017Inventors: Christopher J. Berry, Kaustav Guha, Jose L. Neves, Haifeng Qian, Sourav Saha
-
Publication number: 20170011157Abstract: Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.Type: ApplicationFiled: September 1, 2015Publication date: January 12, 2017Inventors: Christopher J. Berry, Kaustav Guha, Jose L. Neves, Haifeng Qian, Sourav Saha
-
Patent number: 9256705Abstract: A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.Type: GrantFiled: November 26, 2013Date of Patent: February 9, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Paul D. Kartschoke, Adam P. Matheny, Jose L. Neves
-
Patent number: 9223918Abstract: A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.Type: GrantFiled: April 16, 2012Date of Patent: December 29, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Paul D. Kartschoke, Adam P. Matheny, Jose L. Neves
-
Publication number: 20140088948Abstract: A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.Type: ApplicationFiled: November 26, 2013Publication date: March 27, 2014Applicant: International Business Machines CorporationInventors: Paul D. Kartschoke, Adam P. Matheny, Jose L. Neves
-
Publication number: 20130275110Abstract: A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.Type: ApplicationFiled: April 16, 2012Publication date: October 17, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul D. Kartschoke, Adam P. Matheny, Jose L. Neves
-
Patent number: 8108821Abstract: A method for reducing logic and delay within a logic structure that includes searching logic structures to be analyzed, finding a plurality of latches within a logic structure to be analyzed, determining if any respective latches of the plurality of latches have sufficiently positive slack within an input and output path thereof and optionally excluding the respective latches from being analyzed, determining if there is at least one remaining latch to be analyzed, and determining whether inverters are disposed within an input path and an output path of the at least one remaining latch. The method further includes obtaining logic functions of the input path and output path of the at least one remaining latch when inverters are found, modifying the logic functions using DeMorgan's Theorems, determining whether timing violations exist with the modified logic functions, and annotating hardware description language based on the modified logic functions when no timing violations exist.Type: GrantFiled: January 12, 2010Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Jonathan Y. Chen, Jose L. Neves
-
Publication number: 20110173584Abstract: A method for reducing logic and delay within a logic structure that includes searching logic structures to be analyzed, finding a plurality of latches within a logic structure to be analyzed, determining if any respective latches of the plurality of latches have sufficiently positive slack within an input and output path thereof and optionally excluding the respective latches from being analyzed, determining if there is at least one remaining latch to be analyzed, and determining whether inverters are disposed within an input path and an output path of the at least one remaining latch. The method further includes obtaining logic functions of the input path and output path of the at least one remaining latch when inverters are found, modifying the logic functions using DeMorgan's Theorems, determining whether timing violations exist with the modified logic functions, and annotating hardware description language based on the modified logic functions when no timing violations exist.Type: ApplicationFiled: January 12, 2010Publication date: July 14, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan Y. Chen, Jose L. Neves
-
Patent number: 7921398Abstract: A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.Type: GrantFiled: March 13, 2008Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: James J. Curtin, Jose L. Neves, Douglas S. Search
-
Patent number: 7831946Abstract: A wiring structure for clock signals has two or more parallel clock signal wires disposed in adjacent power wire bays that span the distance between the sinks to which the clock signal wires are to be coupled. The parallel clock signal wires are shorted one to another by stubs placed at locations in order to time the clock wiring structure. The delay tuning of the structure is obtained by the discrete movement of wiring stubs between the wiring bays of the pre-defined power grid.Type: GrantFiled: July 31, 2007Date of Patent: November 9, 2010Assignee: International Business Machines CorporationInventors: Rick L. Dennis, Charlie C. Hwang, Jose L. Neves