Patents by Inventor Jose Luis Conesa Lareo

Jose Luis Conesa Lareo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Small-scale, simplified-design frequency multiplier incorporated into integrated circuit
    Patent number: 6020771
    Abstract: A frequency multiplier integrated circuit (IC) has a frequency multiplier 1, an initialization signal generator 2, data sampling generator 3, and a clock generator 4. The frequency multiplier 1 has a timer 17 for calculating a first time between changes of state of an input signal, a time calculator 18 for a second time that a should occur between changes of state in the output signal, and an output signal generator 19 for generating the output signal. The initialization signal generator generates two initialization signals 12 and 13, one being the complement of the other, with a duration greater than 20 msec after an input initialization signal is received.
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: February 1, 2000
    Assignee: Telefonica de Espana, S.A.
    Inventor: Jose Luis Conesa Lareo