Patents by Inventor Jose Luis Neves

Jose Luis Neves has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090106709
    Abstract: A system for improving a logic circuit may include a processor, and a logic circuit analyzer in communication with the processor to model a plurality of nets. The system may also include an interface in communication with the logic circuit analyzer to select a target slack-value for each one of the plurality of nets. The logic circuit analyzer may determine a slack-value for each net. In addition, the logic circuit analyzer may selectively reduce resistive-capacitive delay for each net respectively if the determined slack-value is less than the target slack-value for each respective net.
    Type: Application
    Filed: October 17, 2007
    Publication date: April 23, 2009
    Applicant: INTERNATIONAL BUSINESS CORPORATION
    Inventors: Christopher Carney, Jose Luis Neves, Biagio Pluchino
  • Publication number: 20050108665
    Abstract: A method is provided to speed up timing optimization after placement by parallelizing the optimization step. The method includes performing multiple partitions in the set of timing critical paths such that each partition can be optimized independently in a separate processor. To eliminate the need for inter-processor communication, conditions of timing independence and physical independence are imposed on each partition, thereby defining sub-sets of endpoints and paths associated therewith. The optimizing is performed in parallel by the processors, each of the processors optimizing timing of the paths associated with the endpoints in respective sub-sets. In a preferred embodiment, an endpoint graph is constructed from the list of critical paths, where the endpoint graph has at least one vertex representing critical paths associated with a given endpoint. The partitioning step then includes the step of partitioning the endpoint graph to define sub-sets of vertices.
    Type: Application
    Filed: November 19, 2003
    Publication date: May 19, 2005
    Applicant: International Business Machines Corporation
    Inventors: Jose Luis Neves, Jiyoun Kim
  • Patent number: 6401234
    Abstract: A method and system for re-routing interconnects within an integrated circuit design having blockages and bays is disclosed. A net within the integrated circuit design is initially decomposed into multiple two-paths. The net includes interconnects previously routed by utilizing a Steiner tree routing algorithm. Next, a cost associated with each of the two-paths is calculated. A two-path having a a high cost is subsequently selected and re-routed with a lower cost two-path.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: June 4, 2002
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Rama Gopal Gandham, Jiang Hu, Jose Luis Neves, Stephen Thomas Quay