Patents by Inventor JOSE M. ACEVEDO

JOSE M. ACEVEDO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11809224
    Abstract: Topologies for interconnecting capacitive and inductive elements in a capacitively-coupled rib are described. An example relates to a resonant clock network (RCN) that resonates in response to both a first clock signal having a first phase and a second clock signal having a second phase. The RCN includes at least one rib coupled to at least one spine. The rib includes a first capacitive line configured to receive the first clock signal and provide, via a first capacitor, a first bias current to a first superconducting circuit. The rib further includes a second capacitive line configured to receive the second clock signal and provide, via a second capacitor, a second bias current to a second superconducting circuit. The rib further includes at least one inductive line configured to connect the first capacitive line with the second capacitive line forming a direct connection between the two capacitive lines.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: November 7, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Max Earl Nielsen, Joshua A. Strong, Jose M. Acevedo, Ian G. Thompson
  • Publication number: 20220317722
    Abstract: Topologies for interconnecting capacitive and inductive elements in a capacitively-coupled rib are described. An example relates to a resonant clock network (RCN) that resonates in response to both a first clock signal having a first phase and a second clock signal having a second phase. The RCN includes at least one rib coupled to at least one spine. The rib includes a first capacitive line configured to receive the first clock signal and provide, via a first capacitor, a first bias current to a first superconducting circuit. The rib further includes a second capacitive line configured to receive the second clock signal and provide, via a second capacitor, a second bias current to a second superconducting circuit. The rib further includes at least one inductive line configured to connect the first capacitive line with the second capacitive line forming a direct connection between the two capacitive lines.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 6, 2022
    Inventors: Max Earl NIELSEN, Joshua A. STRONG, Jose M. ACEVEDO, Ian G. THOMPSON
  • Patent number: 10340852
    Abstract: An amplification system can include a bias booster circuit and an amplifier that amplifies an input signal to drive a load. The bias boosting circuit can include a negative bias booster that applies a charge to an input node of the amplifier in response to a negative half-cycle of the input signal that exceeds a boost threshold level. The bias boosting circuit can also include a positive bias booster that discharges the input node of the amplifier during a positive half-cycle of the input signal that exceeds the boost threshold level. The discharging by the positive bias booster is slower than the charging by the negative bias booster to induce a bias voltage increase from a quiescent bias voltage on the input node of the amplifier.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 2, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Sifen Luo, Scott Kent Suko, Jose M. Acevedo, Macarious Salib
  • Publication number: 20190115871
    Abstract: An amplification system can include a bias booster circuit and an amplifier that amplifies an input signal to drive a load. The bias boosting circuit can include a negative bias booster that applies a charge to an input node of the amplifier in response to a negative half-cycle of the input signal that exceeds a boost threshold level. The bias boosting circuit can also include a positive bias booster that discharges the input node of the amplifier during a positive half-cycle of the input signal that exceeds the boost threshold level. The discharging by the positive bias booster is slower than the charging by the negative bias booster to induce a bias voltage increase from a quiescent bias voltage on the input node of the amplifier.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 18, 2019
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: SIFEN LUO, SCOTT KENT SUKO, JOSE M. ACEVEDO, MACARIOUS SALIB