Patents by Inventor Jose M. Grande

Jose M. Grande has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230214234
    Abstract: An information handling system may include a processor and a basic input/output system (BIOS) embodied as executable instructions in non-transitory computer-readable media communicatively coupled to the processor and configured to, when read and executed by the processor, during a Driver Execution Environment of the BIOS, collect an inventory of hardware of the information handling system, generate a configuration-based performance profile based on the inventory and empirical data related to the inventory, present to a user of the information handling system, during a setup utility of the BIOS, a performance workload table setting forth a plurality of performance profiles including the configuration-based performance profile, and in response to the user selecting a performance profile from the plurality of performance profiles, apply the performance profile to a remainder of execution of the BIOS.
    Type: Application
    Filed: January 6, 2022
    Publication date: July 6, 2023
    Applicant: Dell Products L.P.
    Inventors: Jose M. GRANDE, Christopher D. COTE
  • Patent number: 10635554
    Abstract: An information handling system includes a first memory, a second memory, and a central processor. The first memory includes a buffer to store uncorrected no action (UCNA) errors for the second memory. The central processor detects a memory data corruption in the second memory, stores a first UCNA error associated with the memory data corruption in the buffer implemented within the first memory, determines whether the buffer is full, and erases an oldest in time UCNA error from the buffer in response to the buffer being full.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: April 28, 2020
    Assignee: Dell Products, L.P.
    Inventors: David K. Chalfant, Tuyet-Huong Nguyen, Jose M. Grande
  • Publication number: 20200019412
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a plurality of processing units and a plurality of slots, each slot configured to receive a corresponding information handling resource, and a program of instructions embodied in non-transitory computer-readable media and configured to, when read and executed by one of the respective processing units: enumerate the plurality of processing units and the information handling resources populated in the plurality of slots; create a processing unit to information handling resources mapping; and based on the mapping, determine whether a population of information handling resources in the plurality of slots is optimal.
    Type: Application
    Filed: July 12, 2018
    Publication date: January 16, 2020
    Applicant: Dell Products L.P.
    Inventors: Jose M. GRANDE, Wei G. LIU
  • Patent number: 10318455
    Abstract: An information handling system includes a central processing unit, which in turn includes a system memory and a first processor core. The system memory stores Common Platform Error Record (CPER) entries in a queue. The first processor core stores the hardware error in a bank of a machine check bank register of the first processor core, and generates a system management interrupt (SMI) in response to storing the hardware error in the bank. The central processing unit receives the generated SMI, clears CPER entries within the queue of the system memory that are outside a specific timespan before a corrected machine check error indication associated with the generated SMI is received, adds a CPER entry associated with the corrected machine check error indication to the queue of the system memory, and disables SMI generation from the machine check bank number in response to the number of CPER entries exceeding the threshold count.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: June 11, 2019
    Assignee: Dell Products, LP
    Inventors: David K. Chalfant, Tuyet-Huong Nguyen, Jose M. Grande
  • Publication number: 20190026239
    Abstract: An information handling system includes a central processing unit, which in turn includes a system memory and a first processor core. The system memory stores Common Platform Error Record (CPER) entries in a queue. The first processor core stores the hardware error in a bank of a machine check bank register of the first processor core, and generates a system management interrupt (SMI) in response to storing the hardware error in the bank. The central processing unit receives the generated SMI, clears CPER entries within the queue of the system memory that are outside a specific timespan before a corrected machine check error indication associated with the generated SMI is received, adds a CPER entry associated with the corrected machine check error indication to the queue of the system memory, and disables SMI generation from the machine check bank number in response to the number of CPER entries exceeding the threshold count.
    Type: Application
    Filed: July 19, 2017
    Publication date: January 24, 2019
    Inventors: David K. Chalfant, Tuyet-Huong Nguyen, Jose M. Grande
  • Publication number: 20190026202
    Abstract: An information handling system includes a first memory, a second memory, and a central processor. The first memory includes a buffer to store uncorrected no action (UCNA) errors for the second memory. The central processor detects a memory data corruption in the second memory, stores a first UCNA error associated with the memory data corruption in the buffer implemented within the first memory, determines whether the buffer is full, and erases an oldest in time UCNA error from the buffer in response to the buffer being full.
    Type: Application
    Filed: July 19, 2017
    Publication date: January 24, 2019
    Inventors: David K. Chalfant, Tuyet-Huong Nguyen, Jose M. Grande