Patents by Inventor Jose M. Soltero

Jose M. Soltero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6351174
    Abstract: A hold circuit for holding a digital switch, having an input and an output, at the level of the last driven state substantially independently of the output impedance of a circuit driving the digital switch. The hold circuit includes an inverter having an input connected to the output of the digital switch and having an output, and a variable resistor having a port connected to the output of the inverter and having a port connected to the input of the digital switch. In a preferred embodiment, a bus-hold integrated circuit servicing Insulated Gate FET digital switches can be operated from either of two distinct ranges of supply voltage (VCC). The magnitudes of the holding currents for the higher range of VCC are nearly the same as those for the lower range of VCC. This characteristic is achieved by changing the resistance in the feedback path of the bus-hold circuit according to the applied VCC.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: February 26, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Jose M. Soltero, Dale P. Stein
  • Publication number: 20010048332
    Abstract: A hold circuit for holding a digital switch, having an input and an output, at the level of the last driven state substantially independently of the output impedance of a circuit driving the digital switch. The hold circuit includes an inverter having an input connected to the output of the digital switch and having an output, and a variable resistor having a port connected to the output of the inverter and having a port connected to the input of the digital switch.
    Type: Application
    Filed: January 4, 2001
    Publication date: December 6, 2001
    Inventors: Jose M. Soltero, Dale P. Stein
  • Patent number: 6127876
    Abstract: A circuit (12) for reducing positive ground bounce effects on an integrated circuit (10) of the type having an integrated circuit transistor (40) that has reduced conduction when exposed to a positive ground bounce potential includes circuitry responsive to an increase in ground potential to produce a drive current and circuitry for applying the drive current to the integrated circuit transistor (40) to oppose the reduced conduction. The positive ground bounce circuit (12) has a ground bounce sense transistor (56) of same conductivity type as the integrated circuit transistor (40), and a circuit (69) to bias the ground bounce sense transistor (56) normally into conduction to pass a control current. Since ground bounce sense transistor (56) also has reduced conduction when exposed to a positive ground bounce potential, a diode (72) is provided to redirect the control current to the integrated circuit transistor (40), thereby reducing the effects of a positive ground bounce condition.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: October 3, 2000
    Assignee: Texas Instruments Incorporated
    Inventor: Jose M. Soltero