Patents by Inventor Jose M. Valdepenas

Jose M. Valdepenas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High-speed, high-capacity, fault-tolerant error-correcting storage system
    Patent number: 4942579
    Abstract: A storage system for dynamic and trasparent error correction has a number of first individual storage devices for information and a second individual storage device for error code bits that are used to correct the information when one of the storage devices detects an error. Each error code bit is generated from the information at respective bit positions across the first storage devices. Storage device controllers are connected between a user CPU interface and respective storage devices for operating them concurrently. The interface includes an interface CPU for controlling the storage device controllers and translating the interface convention of user CPU requests into the interface convention of the storage devices. A buffer memory is connected to data surface associated with the respective storage devices. The interface CPU includes logic for immediately acknowledging a write to the associated storage device upon the data being placed in the buffer memory.
    Type: Grant
    Filed: February 27, 1989
    Date of Patent: July 17, 1990
    Assignee: Cab-Tek, Inc.
    Inventors: Theodore J. Goodlander, Jose M. Valdepenas, Ricardo E. V. McCaskey, Gerardo Vizcaino