Patents by Inventor Jose Manuel GARCIA GONZALEZ
Jose Manuel GARCIA GONZALEZ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240055464Abstract: An X-ray radiation sensor device may include a direct X-ray conversion layer, a plurality of electrodes to provide an electric charge in response to an interaction of an X-ray photon within the direct X-ray conversion layer, a plurality of pixel sensor arrays, and at least one interposer. The direct X-ray conversion layer and the plurality of electrodes are disposed on the top surface of the interposer(s). The plurality of the pixel sensor arrays is disposed on the bottom surface of the interposer(s), and the interposer(s) is configured to electrically couple each of the pixel sensor arrays to a respective portion of the plurality of electrodes.Type: ApplicationFiled: November 23, 2021Publication date: February 15, 2024Inventors: José Manuel GARCÍA GONZÁLEZ, Joel BERTOMEU MESTRE, Harald ETSCHMAIER, Rafael SERRANO GOTARREDONA
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Patent number: 11711093Abstract: An ADC system comprises a coarse ADC for determining a coarse word representing an input signal, and an incremental ADC for determining a fine word based on a combination of the input signal and a feedback signal. A first combiner generates a first intermediate output word by joining the coarse word and the fine word. A feedback path generates the feedback signal based on the first intermediate output word. A decimation filter generates a second intermediate output word by filtering the first intermediate output word. A correction block determines a correction word based on the coarse word, on the first and the second predetermined number of bits and conversion parameters of the incremental ADC. A second combiner generates an output word by addition of the second intermediate output word and the correction word.Type: GrantFiled: January 30, 2020Date of Patent: July 25, 2023Assignee: AMS INTERNATIONAL AGInventors: José Manuel García González, Thomas Froehlich
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Patent number: 11680969Abstract: A capacitance to digital converter, CDC, has a first and a second reference terminal for receiving first and second reference voltages, a reference block comprising one or more reference charge stores and being coupled to the first and second reference terminals via a first switching block, a scaling block for providing at third and fourth reference terminals downscaled voltages from the first and second reference voltages depending on a scaling factor, first and second measurement terminals for connecting a capacitive sensor element, the first measurement terminal being coupled to the third and fourth reference terminals via a second switching block, and a processing block coupled to the reference block and to the second measurement terminal and being configured to determine a digital output signal based on a charge distribution between the sensor element and the reference block and based on the scaling factor, the output signal representing a capacitance value of the sensor element.Type: GrantFiled: September 25, 2019Date of Patent: June 20, 2023Assignee: ams AGInventors: Rafael Serrano Gotarredona, José Manuel García González
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Publication number: 20230138427Abstract: An ADC system comprises a coarse ADC for determining a coarse word representing an input signal, and an incremental ADC for determining a fine word based on a combination of the input signal and a feedback signal. A first combiner generates a first intermediate output word by joining the coarse word and the fine word. A feedback path generates the feedback signal based on the first intermediate output word. A decimation filter generates a second intermediate output word by filtering the first intermediate output word. A correction block determines a correction word based on the coarse word, on the first and the second predetermined number of bits and conversion parameters of the incremental ADC. A second combiner generates an output word by addition of the second intermediate output word and the correction word.Type: ApplicationFiled: January 30, 2020Publication date: May 4, 2023Inventors: José Manuel GARCÍA GONZÁLEZ, Thomas FROEHLICH
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Publication number: 20220034950Abstract: A capacitance to digital converter, CDC, has a first and a second reference terminal for receiving first and second reference voltages, a reference block comprising one or more reference charge stores and being coupled to the first and second reference terminals via a first switching block, a scaling block for providing at third and fourth reference terminals downscaled voltages from the first and second reference voltages depending on a scaling factor, first and second measurement terminals for connecting a capacitive sensor element, the first measurement terminal being coupled to the third and fourth reference terminals via a second switching block, and a processing block coupled to the reference block and to the second measurement terminal and being configured to determine a digital output signal based on a charge distribution between the sensor element and the reference block and based on the scaling factor, the output signal representing a capacitance value of the sensor element.Type: ApplicationFiled: September 25, 2019Publication date: February 3, 2022Inventors: Rafael SERRANO GOTARREDONA, José Manuel GARCÍA GONZÁLEZ
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Patent number: 11095262Abstract: A circuit arrangement comprises a first input node, a first output node, a sampling capacitor means and a first switching means being switchable between a first switching state and a second switching state. The first switching means is coupled to the sampling capacitor means, the first input node and the first output node in such a way that the sampling capacitor means is conductively connected to the first input node and disconnected from the first output node in the first switching state and the sampling capacitor means is disconnected from the first input node and conductively connected to the first output node in the second switching state. A first charge-storing element is coupled via a second switching means to the first input node in such a way that the charge-storing element is charged in the first switching state and discharged in the second switching state, thereby at least partly compensating current flow for charging the sampling capacitor means in the first switching state.Type: GrantFiled: July 18, 2018Date of Patent: August 17, 2021Assignee: AMS AGInventors: Jose Manuel Garcia Gonzalez, Rafael Serrano Gotarredona
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Patent number: 11031949Abstract: An analog-to-digital converter comprises a first integrator (40), a first converter input (19), a first reference voltage input (34), a capacitor array (68) comprising capacitor elements (171), and a rotation frequency control unit (37) providing a rotation signal (SRO) with at least two different values of a rotation frequency (fR). A first subset of capacitor elements (171) of the capacitor array (68) is coupled to the first converter input (19) and to an input side of the first integrator (40) in a first phase and is coupled to the first reference voltage input (34) and to the input side of the first integrator (40) in a second phase as a function of the rotation signal (SRO).Type: GrantFiled: March 20, 2018Date of Patent: June 8, 2021Assignee: AMS AGInventors: Jose Manuel García González, Rafael Serrano Gotarredona
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Publication number: 20200220510Abstract: A circuit arrangement comprises a first input node, a first output node, a sampling capacitor means and a first switching means being switchable between a first switching state and a second switching state. The first switching means is coupled to the sampling capacitor means, the first input node and the first output node in such a way that the sampling capacitor means is conductively connected to the first input node and disconnected from the first output node in the first switching state and the sampling capacitor means is disconnected from the first input node and conductively connected to the first output node in the second switching state. A first charge-storing element is coupled via a second switching means to the first input node in such a way that the charge-storing element is charged in the first switching state and discharged in the second switching state, thereby at least partly compensating current flow for charging the sampling capacitor means in the first switching state.Type: ApplicationFiled: July 18, 2018Publication date: July 9, 2020Inventors: Jose Manuel GARCIA GONZALEZ, Rafael SERRANO GOTARREDONA
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Patent number: 10338022Abstract: A sensor circuit for measuring a physical or chemical quantity comprises a capacitive sensor. A sense and a base electrode of the sensor form a capacitive element with a capacity depending on the quantity. A common electrode of the sensor forms a first and a second parasitic capacitance together with the sense and the base electrode, respectively. The sensor circuit is adapted to store a charge on the capacitive element and to read out the stored charge via the sense electrode. A buffer element is connected between the sense electrode and the common electrode and adapted to drive the common electrode at a voltage applied to the sense electrode.Type: GrantFiled: March 29, 2016Date of Patent: July 2, 2019Assignee: ams AGInventors: José Manuel García González, Rafael Serrano Gotarredona
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Publication number: 20180136158Abstract: A sensor circuit for measuring a physical or chemical quantity comprises a capacitive sensor. A sense and a base electrode of the sensor form a capacitive element with a capacity depending on the quantity. A common electrode of the sensor forms a first and a second parasitic capacitance together with the sense and the base electrode, respectively. The sensor circuit is adapted to store a charge on the capacitive element and to read out the stored charge via the sense electrode. A buffer element is connected between the sense electrode and the common electrode and adapted to drive the common electrode at a voltage applied to the sense electrode.Type: ApplicationFiled: March 29, 2016Publication date: May 17, 2018Inventors: José Manuel GARCÍA GONZÁLEZ, Rafael SERRANO GOTARREDONA
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Patent number: 9966912Abstract: An amplifier circuit with a differential input and a differential output comprises a first and a second pair of matched transistors having a first threshold voltage and comprising control terminals connected to the differential input. A first and a second pair of triplets of transistors having a second threshold voltage being different from the first threshold voltage is connected to each one of the pairs of matched transistors such that respective current paths are formed with these transistors. The currents are split up to bias current sources and to an output stage such that the current is reused for implementing a class AB operation. Furthermore, a current through bias transistors connected in the current path of the first and the second pair of matched transistors is mirrored to output transistors being arranged in a differential current path of the output stage.Type: GrantFiled: August 20, 2015Date of Patent: May 8, 2018Assignee: ams AGInventors: José Manuel García González, Andreas Fitzi
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Patent number: 9438261Abstract: A capacitance-to-digital converter (10) comprises a capacitor arrangement (30), a converter (1) that is coupled on its input side to the capacitor arrangement (30) and a calibration unit (13) that is coupled on its input side to the converter (1). The capacitor arrangement (30) comprises an input capacitor (16).Type: GrantFiled: April 9, 2015Date of Patent: September 6, 2016Assignee: AMS AGInventors: Jose Manuel Garcia Gonzalez, Joel Bertomeu Mestre, Rafael Serrano Gotarredona
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Publication number: 20150295587Abstract: A capacitance-to-digital converter (10) comprises a capacitor arrangement (30), a converter (1) that is coupled on its input side to the capacitor arrangement (30) and a calibration unit (13) that is coupled on its input side to the converter (1). The capacitor arrangement (30) comprises an input capacitor (16).Type: ApplicationFiled: April 9, 2015Publication date: October 15, 2015Inventors: Jose Manuel GARCIA GONZALEZ, Joel BERTOMEU MESTRE, Rafael SERRANO GOTARREDONA
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Patent number: 8193856Abstract: An amplifier (V) for an integrated circuit amplifier circuit (IC) having a switched capacitor circuit (Cs, Cf) includes a capacitor for frequency compensation (CC1) that is connected in parallel to an amplifier stage (V2). This amplifier is advantageous because at least one second capacitor for frequency compensation (CC2) is selectively connected in parallel to the first capacitor for frequency compensation (CC1) via a switch controlled by a capacitor switching signal (clk).Type: GrantFiled: December 1, 2009Date of Patent: June 5, 2012Assignee: Trident Microsystems (Far East) Ltd.Inventors: José Manuel Garcia González, Norbert Greitschus
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Publication number: 20100171551Abstract: An amplifier (V) for an integrated circuit amplifier circuit (IC) having a switched capacitor circuit (Cs, Cf) includes a capacitor for frequency compensation (CC1) that is connected in parallel to an amplifier stage (V2). This amplifier is advantageous because at least one second capacitor for frequency compensation (CC2) is selectively connected in parallel to the first capacitor for frequency compensation (CC1) via a switch controlled by a capacitor switching signal (clk).Type: ApplicationFiled: December 1, 2009Publication date: July 8, 2010Inventors: José Manuel Garcia González, Norbert Greitschus