Abstract: A slam-shut safety assembly configured to provide redundant safety shutoff in a gas distribution system. The slam-shut safety assembly includes a valve body, a first slam-shut safety device coupled to the valve body, and a second slam-shut safety device coupled to the valve body. The valve body has an inlet, an outlet, and defines a flow path extending between the inlet and the outlet. The first slam-shut safety device is configured to block the flow path at a first position responsive to an overpressure condition or an underpressure condition. The second slam-shut safety device is configured to block the flow path at a second position responsive to the overpressure condition or the underpressure condition.

Abstract: A slam-shut safety assembly configured to provide redundant safety shutoff in a gas distribution system. The slam-shut safety assembly includes a valve body, a first slam-shut safety device coupled to the valve body, and a second slam-shut safety device coupled to the valve body. The valve body has an inlet, an outlet, and defines a flow path extending between the inlet and the outlet. The first slam-shut safety device is configured to block the flow path at a first position responsive to an overpressure condition or an underpressure condition. The second slam-shut safety device is configured to block the flow path at a second position responsive to the overpressure condition or the underpressure condition.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Abstract: A method for configuring a device's cellular data antenna and WiFi antenna to function simultaneously, the method including: in a mobile app, opening the device's WiFi settings and selecting a WiFi network to connect the device to; after connecting the device to the WiFi network, selecting to use cellular network data; adjusting the device's settings to keep the cellular data antenna and WiFi antenna connected at the same time; and selecting media content to be streamed wirelessly to the device via the cellular data antenna while the WiFi antenna is connected.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a load/store superslice, where the load/store superslice includes a set predict array, a first load/store slice, and a second load/store slice. Operation of such a multi-slice processor includes: receiving a two-target load instruction directed to the first load/store slice and a store instruction directed to the second load/store slice; determining a first subset of ports of the set predict array as inputs for an effective address for the two-target load instruction; determining a second subset of ports of the set predict array as inputs for an effective address for the store instruction; and generating, in dependence upon logic corresponding to the set predict array that is less than logic implementing an entire load/store slice, output for performing the two-target load instruction in parallel with generating output for performing the store instruction.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a load/store superslice, where the load/store superslice includes a set predict array, a first load/store slice, and a second load/store slice. Operation of such a multi-slice processor includes: receiving a two-target load instruction directed to the first load/store slice and a store instruction directed to the second load/store slice; determining a first subset of ports of the set predict array as inputs for an effective address for the two-target load instruction; determining a second subset of ports of the set predict array as inputs for an effective address for the store instruction; and generating, in dependence upon logic corresponding to the set predict array that is less than logic implementing an entire load/store slice, output for performing the two-target load instruction in parallel with generating output for performing the store instruction.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a load/store superslice, where the load/store superslice includes a set predict array, a first load/store slice, and a second load/store slice. Operation of such a multi-slice processor includes: receiving a two-target load instruction directed to the first load/store slice and a store instruction directed to the second load/store slice; determining a first subset of ports of the set predict array as inputs for an effective address for the two-target load instruction; determining a second subset of ports of the set predict array as inputs for an effective address for the store instruction; and generating, in dependence upon logic corresponding to the set predict array that is less than logic implementing an entire load/store slice, output for performing the two-target load instruction in parallel with generating output for performing the store instruction.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a load/store superslice, where the load/store superslice includes a set predict array, a first load/store slice, and a second load/store slice. Operation of such a multi-slice processor includes: receiving a two-target load instruction directed to the first load/store slice and a store instruction directed to the second load/store slice; determining a first subset of ports of the set predict array as inputs for an effective address for the two-target load instruction; determining a second subset of ports of the set predict array as inputs for an effective address for the store instruction; and generating, in dependence upon logic corresponding to the set predict array that is less than logic implementing an entire load/store slice, output for performing the two-target load instruction in parallel with generating output for performing the store instruction.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Abstract: Method and system for writing data into a register entry of a processing unit is provided. A logic unit issues an instruction for writing result data into a register entry. At least one functional unit coupled to the logic unit receives the instruction and provides partial result data to be written into the register entry and information regarding the partial result data. A logic circuit coupled to the register entry receives the information regarding the partial result data and writes the partial result data into at least one portion of the register entry based on the received information, the at least one portion of the register entry being determined based on the received information.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Abstract: A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.

Abstract: A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.

Abstract: An apparatus for floating read bitlines of a static random access memory (SRAM) is disclosed. The SRAM includes a first and second SRAM cell columns, a first and second read bitlines, and a multiplexor. The multiplexor is coupled to the first and second SRAM cell columns via the first and second read bitlines, respectively. The multiplexor is capable of selectively transmitting data from the first or second SRAM cell column via the first or second read bitline, respectively, to an output. In addition, the multiplexor allows the first read bitline and/or the second read bitline to remain uncharged when no data are being read from the first SRAM cell column and/or the second SRAM cell column.

Abstract: A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.