Patents by Inventor Jose R. Brunheroto
Jose R. Brunheroto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11734192Abstract: An approach is disclosed that identifies a home node of a data granule. The process is performed by an information handling system (a local node) that retrieves a global virtual address directory. The global virtual address directory maps shared virtual addresses to a number nodes that includes the local node with one of the nodes being the home node. The shared virtual addresses correspond to a plurality of memory addresses that are stored in a shared virtual memory that is shared amongst the plurality of nodes. The approach receives a selected shared virtual address, retrieves, from the global virtual address directory, the home node associated with the selected shared virtual address, and accesses the data granule corresponding to the selected shared virtual address from the home node.Type: GrantFiled: December 10, 2018Date of Patent: August 22, 2023Assignee: International Business Machines CorporationInventors: Charles R. Johns, Jose R. Brunheroto
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Patent number: 11288194Abstract: An approach is disclosed that maintains a consistent view of a virtual address by a local node which writes a first value to the virtual address and, after writing the first value, establishes a snapshot consistency state of the virtual address. The virtual address is shared amongst any number of processes and the processes includes a writing process and other processes that read from the virtual address. After writing the first value, the writing process writes a second value to the virtual address. Even after writing the second value, the first value is still visible to the other processes.Type: GrantFiled: December 12, 2018Date of Patent: March 29, 2022Assignee: International Business Machines CorporationInventors: Charles R. Johns, James A. Kahle, Martin Ohmacht, Changhoan Kim, Jose R. Brunheroto, Constantinos Evangelinos, Abdullah Kayi, Alessandro Morari, James C. Sexton, Patrick D. Siegl
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Patent number: 11200168Abstract: An approach is disclosed that caches distant memories within the storage a local node. The approach provides a memory caching infrastructure that supports virtual addressing by utilizing memory in the local node as a cache of distant memories for data granules. The data granules are accessed along with metadata and an ECC associated with the data granule. The metadata is updated to indicate storage of the selected data granule in the cache.Type: GrantFiled: December 10, 2018Date of Patent: December 14, 2021Assignee: International Business Machines CorporationInventors: Charles R. Johns, Jose R. Brunheroto
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Patent number: 10915460Abstract: An approach is described that accesses data in a shared memory that is shared amongst nodes that include a local node and remote nodes. The local node receives a name corresponding to a named data element in a Coordination Namespace, the Coordination Namespace having been created in a memory distributed amongst the nodes. A hash function is applied to at least a portion of the name with a result of the hash function being a natural node indicator. Data corresponding to the named data element is requested from a natural node identified by the indicator. Based on the request, a response is received from the natural node.Type: GrantFiled: December 12, 2018Date of Patent: February 9, 2021Assignee: International Business Machines CorporationInventors: Ravi Nair, Charles R. Johns, James A. Kahle, Changhoan Kim, Jose R. Brunheroto, Constantinos Evangelinos, Abdullah Kayi, Patrick D. Siegl
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Patent number: 10719903Abstract: Methods for dynamically executing computer code across multiple disparate processing unit architectures are disclosed. During execution of a first portion of computer code on a first processing unit, it is determined that a first dynamic hardware behavior of a plurality of dynamic hardware behaviors will occur at a subsequent point in time, based on a second dynamic hardware behavior that is occurring. The methods include determining to execute code corresponding to the first dynamic hardware behavior on a second processing unit, rather than the first processing unit, and scheduling computer program code corresponding to the first dynamic hardware behavior to execute on the second processing unit rather than the first processing unit. Upon completion of execution of the computer code corresponding to the first dynamic hardware behavior, a remaining portion of the computer code is scheduled to execute on the first processing unit.Type: GrantFiled: December 22, 2017Date of Patent: July 21, 2020Assignee: International Business Machines CorporationInventors: Fausto Artico, Jose R. Brunheroto, Juan Gonzalez Garcia, Nelson Mimura Gonzalez
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Publication number: 20200192799Abstract: An approach is disclosed that maintains a consistent view of a virtual address by a local node which writes a first value to the virtual address and, after writing the first value, establishes a snapshot consistency state of the virtual address. The virtual address is shared amongst any number of processes and the processes includes a writing process and other processes that read from the virtual address. After writing the first value, the writing process writes a second value to the virtual address. Even after writing the second value, the first value is still visible to the other processes.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Inventors: Charles R. Johns, James A. Kahle, Martin Ohmacht, Changhoan Kim, Jose R. Brunheroto, Constantinos Evangelinos, Abdullah Kayi, Alessandro Morari, James C. Sexton, Patrick D. Siegl
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Publication number: 20200192819Abstract: An approach is described that accesses data in a shared memory that is shared amongst nodes that include a local node and remote nodes. The local node receives a name corresponding to a named data element in a Coordination Namespace, the Coordination Namespace having been created in a memory distributed amongst the nodes. A hash function is applied to at least a portion of the name with a result of the hash function being a natural node indicator. Data corresponding to the named data element is requested from a natural node identified by the indicator. Based on the request, a response is received from the natural node.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Inventors: Ravi Nair, Charles R. Johns, James A. Kahle, Changhoan Kim, Jose R. Brunheroto, Constantinos Evangelinos, Abdullah Kayi, Patrick D. Siegl
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Publication number: 20200183854Abstract: An approach is disclosed that identifies a home node of a data granule. The process is performed by an information handling system (a local node) that retrieves a global virtual address directory. The global virtual address directory maps shared virtual addresses to a number nodes that includes the local node with one of the nodes being the home node. The shared virtual addresses correspond to a plurality of memory addresses that are stored in a shared virtual memory that is shared amongst the plurality of nodes. The approach receives a selected shared virtual address, retrieves, from the global virtual address directory, the home node associated with the selected shared virtual address, and accesses the data granule corresponding to the selected shared virtual address from the home node.Type: ApplicationFiled: December 10, 2018Publication date: June 11, 2020Inventors: Charles R. Johns, Jose R. Brunheroto
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Publication number: 20200183840Abstract: An approach is disclosed that caches distant memories within the storage a local node. The approach provides a memory caching infrastructure that supports virtual addressing by utilizing memory in the local node as a cache of distant memories for data granules. The data granules are accessed along with metadata and an ECC associated with the data granule. The metadata is updated to indicate storage of the selected data granule in the cache.Type: ApplicationFiled: December 10, 2018Publication date: June 11, 2020Inventors: Charles R. Johns, Jose R. Brunheroto
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Publication number: 20200183836Abstract: An approach is disclosed that maintains a status of a data granule. A local node maintains the status by tracking a set of state information associated with the data granule using a system memory metadata. The state information indicates whether the data granule that is associated with a block of memory is currently stored in a physical address on the local node. An interrupt is generated in response to detecting an access of the data granule when the data granule associated with the block of memory is not stored at the physical address on the local node.Type: ApplicationFiled: December 10, 2018Publication date: June 11, 2020Inventors: Charles R. Johns, Jose R. Brunheroto
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Patent number: 10540737Abstract: Methods for estimating accelerator performance for dynamic hardware behaviors are disclosed. Computer program code to be executed on a first processing unit is received, and an execution of the computer code on the first processing unit is monitored to determine a plurality of performance characteristics. A plurality of dynamic hardware behaviors is determined by applying a clustering algorithm to the performance characteristics, and an equivalent accelerator portion of computer code to be executed on a second processing unit is generated by translating a set of instructions in a first portion of computer code corresponding to a first one of the plurality of dynamic hardware behaviors to an equivalent set of instructions to be executed on the second processing unit. An estimated measure of performance for executing the equivalent accelerator portion on the second processing unit is determined for the first one of the plurality of dynamic hardware behaviors.Type: GrantFiled: December 22, 2017Date of Patent: January 21, 2020Assignee: International Business Machines CorporationInventors: Fausto Artico, Jose R. Brunheroto, Juan Gonzalez Garcia, Nelson Mimura Gonzalez
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Publication number: 20190197653Abstract: Methods for estimating accelerator performance for dynamic hardware behaviors are disclosed. Computer program code to be executed on a first processing unit is received, and an execution of the computer code on the first processing unit is monitored to determine a plurality of performance characteristics. A plurality of dynamic hardware behaviors is determined by applying a clustering algorithm to the performance characteristics, and an equivalent accelerator portion of computer code to be executed on a second processing unit is generated by translating a set of instructions in a first portion of computer code corresponding to a first one of the plurality of dynamic hardware behaviors to an equivalent set of instructions to be executed on the second processing unit. An estimated measure of performance for executing the equivalent accelerator portion on the second processing unit is determined for the first one of the plurality of dynamic hardware behaviors.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventors: Fausto ARTICO, Jose R. Brunheroto, Juan Gonzalez Garcia, Nelson Mimura Gonzalez
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Publication number: 20190197652Abstract: Methods for dynamically executing computer code across multiple disparate processing unit architectures are disclosed. During execution of a first portion of computer code on a first processing unit, it is determined that a first dynamic hardware behavior of a plurality of dynamic hardware behaviors will occur at a subsequent point in time, based on a second dynamic hardware behavior that is occurring. The methods include determining to execute code corresponding to the first dynamic hardware behavior on a second processing unit, rather than the first processing unit, and scheduling computer program code corresponding to the first dynamic hardware behavior to execute on the second processing unit rather than the first processing unit. Upon completion of execution of the computer code corresponding to the first dynamic hardware behavior, a remaining portion of the computer code is scheduled to execute on the first processing unit.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventors: Fausto ARTICO, Jose R. BRUNHEROTO, Juan Gonzalez GARCIA, Nelson Mimura GONZALEZ
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Patent number: 9971713Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.Type: GrantFiled: April 30, 2015Date of Patent: May 15, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
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Patent number: 9417882Abstract: There is provided a processor implemented method for controlling a lock-stepped cohort. The method includes receiving instructions for each of a first lane and a second lane. The first lane is for the lock-stepped cohort and the second lane is for another cohort. The method further includes detecting a condition in which a first instruction at the first lane will have a higher latency than a second instruction at the second lane. The method also includes setting an indicator indicating where the first lane encountered the first instruction. The method additionally includes setting the first lane to inactive, while keeping the second lane active. The method further includes setting the first lane to active on a subsequent opportunity to execute said first instruction.Type: GrantFiled: December 23, 2013Date of Patent: August 16, 2016Assignee: International Business Machines CorporationInventors: Jose R. Brunheroto, Chen-Yong Cher, Hubertus Franke, Jamin Naghmouchi
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Publication number: 20160011996Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.Type: ApplicationFiled: April 30, 2015Publication date: January 14, 2016Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
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Patent number: 9081501Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).Type: GrantFiled: January 10, 2011Date of Patent: July 14, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
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Publication number: 20150178089Abstract: There is provided a processor implemented method for controlling a lock-stepped cohort. The method includes receiving instructions for each of a first lane and a second lane. The first lane is for the lock-stepped cohort and the second lane is for another cohort. The method further includes detecting a condition in which a first instruction at the first lane will have a higher latency than a second instruction at the second lane. The method also includes setting an indicator indicating where the first lane encountered the first instruction. The method additionally includes setting the first lane to inactive, while keeping the second lane active. The method further includes setting the first lane to active on a subsequent opportunity to execute said first instruction.Type: ApplicationFiled: December 23, 2013Publication date: June 25, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jose R. Brunheroto, Chen-Yong Cher, Hubertus Franke, Jamin Naghmouchi
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Publication number: 20110219208Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).Type: ApplicationFiled: January 10, 2011Publication date: September 8, 2011Applicant: International Business Machines CorporationInventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
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Patent number: 7908439Abstract: Disclosed are a method and apparatus for replacing pre-fetched data in a pre-fetch cache. In one embodiment, each line of the pre-fetch cache will be accessed at most M times. A line accessed M times can be evicted from the cache without any performance loss. In this embodiment, a counter is added to each pre-fetch data line to track how many times it has been accessed. In another embodiment, a displacement bit is added to each pre-fetch data line, and when a defined portion of the data line is accessed, this bit is set to a given value, indicating that the line can be evicted.Type: GrantFiled: June 25, 2007Date of Patent: March 15, 2011Assignee: International Business Machines CorporationInventors: Jose R. Brunheroto, Valentina Salapura