Patents by Inventor Jose Rebollo

Jose Rebollo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11688774
    Abstract: A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: June 27, 2023
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Ignacio Cortes Mayol, Philippe Godignon, Victor Soler, Jose Rebollo
  • Patent number: 11527626
    Abstract: A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: December 13, 2022
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Ignacio Cortes Mayol, Philippe Godignon, Victor Soler, Jose Rebollo
  • Publication number: 20220140093
    Abstract: A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.
    Type: Application
    Filed: January 11, 2022
    Publication date: May 5, 2022
    Inventors: Ignacio Cortes Mayol, Philippe Godignon, Victor Soler, Jose Rebollo
  • Publication number: 20220140092
    Abstract: A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Inventors: Ignacio Cortes Mayol, Philippe Godignon, Victor Soler, Jose Rebollo