Abstract: Techniques include retrieving a first structural netlist (SN1) that indicates electronic components, values of programmable parameters, and connections for a first electronic circuit, and retrieving a first placed and routed netlist (PR1) that indicates physical placement of the electronic components and physical routing of connections for SN1. Also retrieved is a second structural netlist (SN2) for a different second electronic circuit. For each component in SN2, a matching component, if any, is found in SN1 based on type of component and inputs that are output from other matching components. A different second placed and routed netlist (PR2) is generated for the second circuit by deriving new placement and routing for only for non-matching components in SN2.

Abstract: Techniques include retrieving a first structural netlist (SN1) that indicates electronic components, values of programmable parameters, and connections for a first electronic circuit, and retrieving a first placed and routed netlist (PR1) that indicates physical placement of the electronic components and physical routing of connections for SN1. Also retrieved is a second structural netlist (SN2) for a different second electronic circuit. For each component in SN2, a matching component, if any, is found in SN1 based on type of component and inputs that are output from other matching components. A different second placed and routed netlist (PR2) is generated for the second circuit by deriving new placement and routing for only for non-matching components in SN2.

Abstract: Techniques include retrieving a first structural netlist (SN1) that indicates electronic components, values of programmable parameters, and connections for a first electronic circuit, and retrieving a first placed and routed netlist (PR1) that indicates physical placement of the electronic components and physical routing of connections for SN1. Also retrieved is a second structural netlist (SN2) for a different second electronic circuit. For each component in SN2, a matching component, if any, is found in SN1 based on type of component and inputs that are output from other matching components without regard to value of the programmable parameter. A different second placed and routed netlist (PR2) is generated for the second circuit by including, from PR1, all matching components and connections, updated value of the programmable parameter from SN2, and by deriving new placement and routing for non-matching components in SN2. An electronic circuit is constructed according to PR2.

Abstract: Techniques include retrieving a first structural netlist (SN1) that indicates electronic components, values of programmable parameters, and connections for a first electronic circuit, and retrieving a first placed and routed netlist (PR1) that indicates physical placement of the electronic components and physical routing of connections for SN1. Also retrieved is a second structural netlist (SN2) for a different second electronic circuit. For each component in SN2, a matching component, if any, is found in SN1 based on type of component and inputs that are output from other matching components without regard to value of the programmable parameter. A different second placed and routed netlist (PR2) is generated for the second circuit by including, from PR1, all matching components and connections, updated value of the programmable parameter from SN2, and by deriving new placement and routing for non-matching components in SN2. An electronic circuit is constructed according to PR2.

Abstract: An interactive incremental synthesis flow for integrated circuit design includes performing a full synthesis [304] of a circuit design to produce an elaborated netlist and synthesized netlist; based on the elaborated netlist and synthesized netlist, automatically partitioning [306] the circuit design into invariant cone regions whose functionality do not change during synthesis; and performing an incremental synthesis [308] each time a change is made to the circuit design.

Abstract: An interactive incremental synthesis flow for integrated circuit design includes performing a full synthesis [304] of a circuit design to produce an elaborated netlist and synthesized netlist; based on the elaborated netlist and synthesized netlist, automatically partitioning [306] the circuit design into invariant cone regions whose functionality do not change during synthesis; and performing an incremental synthesis [308] each time a change is made to the circuit design.

Abstract: The disclosed embodiments provide techniques for reducing address-translation latency and the serialization latency of combined TLB and data cache misses in a coherent shared-memory system. For instance, the last-level TLB structures of two or more multiprocessor nodes can be configured to act together as either a distributed shared last-level TLB or a directory-based shared last-level TLB. Such TLB-sharing techniques increase the total amount of useful translations that are cached by the system, thereby reducing the number of page-table walks and improving performance. Furthermore, a coherent shared-memory system with a shared last-level TLB can be further configured to fuse TLB and cache misses such that some of the latency of data coherence operations is overlapped with address translation and data cache access latencies, thereby further improving the performance of memory operations.

Abstract: A decoupled memory execution verification method is provided that includes executing load and store commands separately using an appropriately programmed computer, where the load and store commands are independent of correctness, where the load commands and the store commands are re-executed in-order at memory retirement to verify correctness, where an energy efficient power decoupled execution of memory (e-PDEMI) is provided.

Abstract: The disclosed embodiments provide techniques for reducing address-translation latency and the serialization latency of combined TLB and data cache misses in a coherent shared-memory system. For instance, the last-level TLB structures of two or more multiprocessor nodes can be configured to act together as either a distributed shared last-level TLB or a directory-based shared last-level TLB. Such TLB-sharing techniques increase the total amount of useful translations that are cached by the system, thereby reducing the number of page-table walks and improving performance. Furthermore, a coherent shared-memory system with a shared last-level TLB can be further configured to fuse TLB and cache misses such that some of the latency of data coherence operations is overlapped with address translation and data cache access latencies, thereby further improving the performance of memory operations.