Patents by Inventor Jose Renau Ardevol

Jose Renau Ardevol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9003163
    Abstract: The disclosed embodiments provide techniques for reducing address-translation latency and the serialization latency of combined TLB and data cache misses in a coherent shared-memory system. For instance, the last-level TLB structures of two or more multiprocessor nodes can be configured to act together as either a distributed shared last-level TLB or a directory-based shared last-level TLB. Such TLB-sharing techniques increase the total amount of useful translations that are cached by the system, thereby reducing the number of page-table walks and improving performance. Furthermore, a coherent shared-memory system with a shared last-level TLB can be further configured to fuse TLB and cache misses such that some of the latency of data coherence operations is overlapped with address translation and data cache access latencies, thereby further improving the performance of memory operations.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: April 7, 2015
    Assignee: Oracle International Corporation
    Inventors: Pranay Koka, Michael O. McCracken, Herbert D. Schwetman, Jr., David A. Munday, Jose Renau Ardevol
  • Publication number: 20140325156
    Abstract: A decoupled memory execution verification method is provided that includes executing load and store commands separately using an appropriately programmed computer, where the load and store commands are independent of correctness, where the load commands and the store commands are re-executed in-order at memory retirement to verify correctness, where an energy efficient power decoupled execution of memory (e-PDEMI) is provided.
    Type: Application
    Filed: December 17, 2012
    Publication date: October 30, 2014
    Inventor: Jose Renau Ardevol
  • Publication number: 20140013074
    Abstract: The disclosed embodiments provide techniques for reducing address-translation latency and the serialization latency of combined TLB and data cache misses in a coherent shared-memory system. For instance, the last-level TLB structures of two or more multiprocessor nodes can be configured to act together as either a distributed shared last-level TLB or a directory-based shared last-level TLB. Such TLB-sharing techniques increase the total amount of useful translations that are cached by the system, thereby reducing the number of page-table walks and improving performance. Furthermore, a coherent shared-memory system with a shared last-level TLB can be further configured to fuse TLB and cache misses such that some of the latency of data coherence operations is overlapped with address translation and data cache access latencies, thereby further improving the performance of memory operations.
    Type: Application
    Filed: June 12, 2012
    Publication date: January 9, 2014
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Pranay Koka, Michael O. McCracken, Herbert D. Schwetman, JR., David A. Munday, Jose Renau Ardevol