Abstract: Matrix recovery and link maintenance for a signaling node in an SS7 network. The signaling node comprises a planar redundant switching matrix with master and standby sides. End devices for trunk interfacing and channel data control receive data and timing from the master side, de-coupled from data and timing paths of the standby side. In steady-state, revenue traffic between the SS7 network and the signaling node runs on the master side in a pulse code modulated (PCM) form. Test channels are set up on both sides. Test patterns are propagated on the test channels for monitoring failures of timing path, PCM data, and device communication. When a failure condition is detected on the master side, the signaling node transmits idle signaling to the network, so that the revenue traffic is suspended and the link is maintained in an in-service state.

Abstract: A switching matrix interface for a delivery unit that transports network data on telecommunications media to a switching matrix. The interface shares a “common building block” format with other modules of the delivery unit. Specifically, a bus interface port of the interface transports network data from the delivery unit (prior to switching) and back to the delivery unit (after switching) in a common data format. Buffers provide timing and align for transport to and from the switching matrix. The interface provides a path verification scheme using a superframe format for path integrity bits.

Abstract: A message transport network (10) is provided for high speed switching between processing elements (72, 80). Clusters of low speed processing elements (72) may be connected to the message transport network (10) through a transport node controller (78). The transport node controller (78) and the high speed processors (80) are connected to the gateways (82). A pair of gateways (82) may be connected through a transport interchange node (106) to allow communication between processors (72, 80) associated with the gateways (82). A transport interchange supervisor (98) maintains a record of the status of each gateway (82) and generates commands to form connection between gateways (82) in the transport interchange node (106). A maintenance controller (102) and system maintenance processor (76) oversee the validity of the data being passed through the system on paths independent of the data transfer paths.