Abstract: The present subject matter relates to an electronic system comprising gated circuitry, a first regulator circuit directly coupled to the gated circuitry, always-on circuitry, a second regulator circuit directly coupled to the always-on circuitry, and a switch circuit coupled between an output of the first regulator circuit and an output of the second regulator circuit. The always-on circuitry includes control logic configured to activate the second regulator circuit and deactivate the first regulator circuit and the switch circuit in a sleep mode and activate the first regulator circuit and the switch circuit in an active mode.

Abstract: A switched capacitor voltage converter is provided that includes an array of switches configured to alternately switch multiple capacitors between a charge configuration in which the multiple capacitors are coupled in series with each other and in parallel with the source voltage and a discharge configuration in which a first set of capacitors having n capacitors are coupled in parallel with each other and in series with the load and a second set of capacitors having m capacitors coupled in parallel with the load.

Abstract: A switched capacitor voltage converter is provided that includes an array of switches configured to alternately switch multiple capacitors between a charge configuration in which the multiple capacitors are coupled in series with each other and in parallel with the source voltage and a discharge configuration in which a first set of capacitors having n capacitors are coupled in parallel with each other and in series with the load and a second set of capacitors having m capacitors coupled in parallel with the load.

Abstract: This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel VN level instead of the line/reference amplifier level. The pixel signal voltage VN and offset voltage VNS are read sequentially, eliminating the differential structure. Interference rejection, usually achieved by a differential signal, is obtained by using a CDS (Correlated Double Sampler) in the same way as in the prior art.

Abstract: This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel VN level instead of the line/reference amplifier level. The pixel signal voltage VN and offset voltage VNS are read sequentially, eliminating the differential structure. Interference rejection, usually achieved by a differential signal, is obtained by using a CDS (Correlated Double Sampler) in the same way as in the prior art.

Abstract: This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel VN level instead of the line/reference amplifier level. The pixel signal voltage VN and offset voltage VNS are read sequentially, eliminating the differential structure. Interference rejection, usually achieved by a differential signal, is obtained by using a CDS (Correlated Double Sampler) in the same way as in the prior art.