Abstract: The instant disclosure relates to methods for preventing, controlling and/or inhibiting the rare events of adventitious viral infection or viral replication/amplification after reactivation of latent viral infection during cell culture in the manufacturing process of cell-based drug products, including CAR T cell drug products. Also provided are in vitro cell culture models for HHV-6 latent infection and methods of making the same.

Abstract: The present invention relates a process for separating H2, preferably both H2 and CH4, from a gas mixture comprising H2 and CH4 by means of a series of selective membrane units that avoids compressors and vacuums as well as an apparatus for carrying out said separation.

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Abstract: Techniques and mechanisms for a processor to efficiently identify a circuit resource as being a source of data poisoning. In an embodiment, metadata is communicated, in association with a communication of poisoned data to which the metadata pertains, to a first circuit block of a processor. The metadata indicates a poisoned state of the data, wherein the metadata identifies a second circuit block—which is included in or coupled to the processor—as being a poisoner of the data. Based on the metadata, the first circuit block generates a fault message which identifies the second circuit block as the poisoner of the data. In another embodiment, the processor further comprises the second circuit block, which poisons the data (based on the detection of an error condition) by providing in the metadata a unique identifier which is assigned to the second circuit block.

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Abstract: Techniques and mechanisms for a processor to efficiently identify a circuit resource as being a source of data poisoning. In an embodiment, metadata is communicated, in association with a communication of poisoned data to which the metadata pertains, to a first circuit block of a processor. The metadata indicates a poisoned state of the data, wherein the metadata identifies a second circuit block—which is included in or coupled to the processor—as being a poisoner of the data. Based on the metadata, the first circuit block generates a fault message which identifies the second circuit block as the poisoner of the data. In another embodiment, the processor further comprises the second circuit block, which poisons the data (based on the detection of an error condition) by providing in the metadata a unique identifier which is assigned to the second circuit block.

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Abstract: A system for processing biological specimens mounted on microscope slides by adding and removing processing fluids from microscope slides by means of capillary action using a slide holder capable of holding multiple microscope slides, and a spacer positioned in between two slides of a slide pair to create a capillary gap. A capillary gap adjuster can be used to pinch and release one end of the slide pair to create a pulsatile action to mix the reagent within the capillary gap. The system may further include a reagent holder, an absorbent pad, a series of reagent baths, and an incubator for holding one or more slide holders.

Abstract: A vehicle driver exercising system includes a pair of hand exercising members each removably engaged with a steering wheel. The hand exercising members each include a clip having an inner surface and an outer surface. The clip receives the steering wheel and a base is attached to the outer surface. A housing is slidably mounted to an upper surface of the base and has an outer flange is movable between an extended position extended upwardly from and spaced away from the base or a collapsed position abutting the base. A biasing member is positioned in the base and biases the housing toward the extended position.

Abstract: A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank.

Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Abstract: Hardware processors and methods to perform self-monitoring diagnostics to predict and detect failure are described. In one embodiment, a hardware processor includes a plurality of cores, and a diagnostic hardware unit to isolate a core of the plurality of cores at run-time, perform a stress test on an isolated core, determine a stress factor from a result of the stress test, and store the stress factor in a data storage device.

Abstract: Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

Abstract: An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.

Abstract: Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.

Abstract: Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Abstract: A system for processing biological specimens mounted on microscope slides by adding and removing processing fluids from microscope slides by means of capillary action using a slide holder capable of holding multiple microscope slides, and a spacer positioned in between two slides of a slide pair to create a capillary gap. A capillary gap adjuster can be used to pinch and release one end of the slide pair to create a pulsatile action to mix the reagent within the capillary gap. The system may further include a reagent holder, an absorbent pad, a series of reagent baths, and an incubator for holding one or more slide holders.