Patents by Inventor Josef A Dvorak

Josef A Dvorak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8677049
    Abstract: A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: March 18, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mahadev S. Deshpande, Ronny L. Arnold, Josef A. Dvorak, Paul L. Rogers
  • Patent number: 8461902
    Abstract: A multiplexer (MUX) circuit with balanced select line loading is provided. The MUX circuit includes a plurality of 2:1 MUX units coupled together in a multistage cascading arrangement, along with a selection module coupled to the MUX units. The MUX units are arranged in an initial MUX stage, at least one intermediate MUX stage coupled to and following the initial MUX stage, and a final MUX stage coupled to and following the at least one intermediate MUX stage. Each MUX unit is controlled with a respective select bit input value provided by the selection module. The selection module controls the operation of the MUX units in the initial MUX stage with a first plurality of different select bits, controls the operation of the MUX units in the at least one intermediate MUX stage with a second plurality of different select bits, and controls the operation of the final MUX stage with a devoted select bit.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: June 11, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Josef A. Dvorak, Edward Chang, Douglas R. Williams
  • Publication number: 20120194250
    Abstract: A multiplexer (MUX) circuit with balanced select line loading is provided. The MUX circuit includes a plurality of 2:1 MUX units coupled together in a multistage cascading arrangement, along with a selection module coupled to the MUX units. The MUX units are arranged in an initial MUX stage, at least one intermediate MUX stage coupled to and following the initial MUX stage, and a final MUX stage coupled to and following the at least one intermediate MUX stage. Each MUX unit is controlled with a respective select bit input value provided by the selection module. The selection module controls the operation of the MUX units in the initial MUX stage with a first plurality of different select bits, controls the operation of the MUX units in the at least one intermediate MUX stage with a second plurality of different select bits, and controls the operation of the final MUX stage with a devoted select bit.
    Type: Application
    Filed: January 27, 2011
    Publication date: August 2, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Josef A. DVORAK, Edward CHANG, Douglas R. WILLIAMS
  • Publication number: 20100262750
    Abstract: A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address.
    Type: Application
    Filed: April 13, 2009
    Publication date: October 14, 2010
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mahadev S. Deshpande, Ronny L. Arnold, Josef A. Dvorak, Paul L. Rogers
  • Patent number: 6535989
    Abstract: An apparatus for producing one or more clock signals comprises a plurality of delay elements sequentially connected and logic circuitry connected to several of the plurality of delay elements. A clock signal fed through the plurality of delay elements produces multiple delayed versions of the clock signal. Logic circuitry selects and combines the delayed clock signal versions to produce one or more output clock signals, each having a frequency that is a selected fraction of the input clock signal. An associated method delays the input clock signal N times sequentially for a natural number N. then selects a series of time splices of the delayed clock signals to produce an output clock signal. In some implementations the input clock signal can be referenced to a reference clock signal. The output clock signal frequency can be set to (N/M)×fref, for a natural number M and reference clock signal frequency fref.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: March 18, 2003
    Assignee: Hewlett-Packard Company
    Inventors: Josef A Dvorak, Ricky L Pettit, David B Hollenbeck, Kent R Townley
  • Patent number: 6092559
    Abstract: A device for controlling warp threads in weaving of leno fabrics on a weaving device, such as a loom, has a guide mechanism for stationary warp threads and rotating warp threads. The guide mechanism includes a system of reversibly movable needles with eyes for passage of the stationary warp threads and a reversibly movable guide member for the stationary warp threads that is driven in association with the needles. The guide mechanism also has a vertically adjustable member with a plurality of oblique slots for the rotating warp threads for effecting side-to-side movement thereof as a result of vertical movement of the rotating warp threads within the slots, and an adjustably mounted compensation mechanism.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: July 25, 2000
    Assignees: BP Amoco Corporation, Vyzkummy Ustav Textilnich Stroju Liberec A.S.
    Inventors: Josef Dvorak, Jiri Mylnar, Miroslav Rydval, Petr Karel
  • Patent number: 5641002
    Abstract: A method of insertion of the weft thread into the shed of an air-operated jet loom in which a main stream of air supplied to an end of a direct pick channel in a swinging loom reed is supplemented at regular length intervals along the whole length of the direct pick channel by ancillary air streams oriented obliquely in the direction of the weft thread insertion into an open side of the direct pick channel through which the air streams move the weft thread. A device for carrying out the above method of insertion of the weft thread into the shed of a loom has a loom reed adapted to swing on an axis and is equipped with a direct pick channel, with a main pick jet related thereto on one lateral side, and with a plurality of ancillary jets situated at uniform intervals along its length and each ancillary jet having an outlet apertures oriented obliquely into the open side of the pick channel of the loom reed.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: June 24, 1997
    Assignee: Vyzkumy Ustav Textilnich Stroju Liberec A.S.
    Inventors: Petr Jirasko, Zdenek Volansky, Josef Dvorak, Zdenek Koloc
  • Patent number: 4175474
    Abstract: Variable displacement cam driven piston pump having means for the stepless adjustment of the length of the pump stroke. The stroke adjusting means has pivotally mounted spaced parallel levers, the levers being interposed between the cam and the piston of the pump, the levers being mutually coupled in their movement by a means adjustably arranged along the length of said levers, said levers being disposed on the opposite sides of a plane defined by the contact points between the lever coupling means and the levers.
    Type: Grant
    Filed: November 15, 1977
    Date of Patent: November 27, 1979
    Assignee: Elitex, Koncern textilniho strojirenstvi
    Inventors: Ladislav Sevcik, Josef Dvorak, Jiri Mlynar