Patents by Inventor Josef Bock

Josef Bock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080227261
    Abstract: The invention relates to a method for fabricating a transistor structure, comprising at least a first and a second bipolar transistor having different collector widths. The invention is distinguished by the fact that all junctions between differently doped regions have a sharp interface. In this case, by way of example, a first collector region 2.1 is suitable for a high-frequency transistor with high limiting frequencies fT and a second collector region 2.2 is suitable for a high-voltage transistor with increased breakdown voltages.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 18, 2008
    Inventors: Josef Bock, Rudolf Lachner, Thomas Meister, Reinhard Stengl, Herbert Schafer, Martin Seck
  • Patent number: 7420228
    Abstract: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region, and an emitter region of the first conduction type which is provided above the base region on the side remote from the collection region. A carbon-doped semiconductor region is provided on the first side alongside the collector region. The bipolar transistor is characterized in that the carbon-doped semiconductor region has a carbon concentration of 1019-1021 cm?3 and the base region has a smaller cross section than the collector region and the collector region has, in the overlap region with the base region, a region having an increased doping compared with the remaining region.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: September 2, 2008
    Assignee: Infineon Technologies AG
    Inventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
  • Publication number: 20080102593
    Abstract: A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.
    Type: Application
    Filed: October 27, 2006
    Publication date: May 1, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Meister, Herbert Schafer, Josef Bock, Rudolf Lachner
  • Patent number: 7285470
    Abstract: The invention relates to a method for producing a bipolar semiconductor element, especially a bipolar transistor, and a corresponding bipolar semiconductor component.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: October 23, 2007
    Assignee: Infineon Technologies AG
    Inventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
  • Patent number: 7256472
    Abstract: A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: August 14, 2007
    Assignee: Infineon Technologies AG
    Inventors: Josef Bock, Thomas Meister, Andriy Romanyuk, Herbert Schäfer
  • Patent number: 7105415
    Abstract: The invention relates to a method for producing a bipolar transistor. A semiconductor substrate is provided that encompasses a collector area of a first conductivity type, which is embedded therein and is bare towards the top. A monocrystalline base area is provided and a base-connecting area of the second conductivity type is provided above the base area. An insulating area is provided above the base-connecting area and a window is formed in the insulating area and the base-connecting area so as to at least partly expose the base area. An insulating sidewall spacer is provided in the window in order to insulate the base-connecting area. An emitter layer which forms a monocrystalline emitter area above the base area and a polycrystalline emitter area above the insulating area and the sidewall spacer is differentially deposited and structured, and a tempering step is carried out.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: September 12, 2006
    Assignee: Infineon Technologies AG
    Inventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
  • Publication number: 20060097352
    Abstract: A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance.
    Type: Application
    Filed: July 11, 2003
    Publication date: May 11, 2006
    Inventors: Josef Bock, Thomas Meister, Andriy Romanyuk, Herbert Schafer
  • Publication number: 20060040456
    Abstract: The invention relates to a method for producing a bipolar semiconductor element, especially a bipolar transistor, and a corresponding bipolar semiconductor component.
    Type: Application
    Filed: September 30, 2005
    Publication date: February 23, 2006
    Inventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
  • Publication number: 20060038258
    Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.
    Type: Application
    Filed: October 20, 2005
    Publication date: February 23, 2006
    Inventors: Josef Bock, Thomas Meister, Reinhard Stengl, Hertbert Schafer
  • Publication number: 20060040453
    Abstract: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region, and an emitter region of the first conduction type which is provided above the base region on the side remote from the collection region. A carbon-doped semiconductor region is provided on the first side alongside the collector region. The bipolar transistor is characterized in that the carbon-doped semiconductor region has a carbon concentration of 1019-1021 cm?3 and the base region has a smaller cross section than the collector region and the collector region has, in the overlap region with the base region, a region having an increased doping compared with the remaining region.
    Type: Application
    Filed: October 7, 2005
    Publication date: February 23, 2006
    Inventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
  • Publication number: 20060009002
    Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.
    Type: Application
    Filed: October 24, 2003
    Publication date: January 12, 2006
    Inventors: Josef Bock, Rudolf Lachner, Thomas Meister, Reinhard Stengl, Herbert Schafer, Martin Seck
  • Publication number: 20050233536
    Abstract: The invention relates to a method for producing a bipolar transistor. A semiconductor substrate is provided that encompasses a collector area of a first conductivity type, which is embedded therein and is bare towards the top. A monocrystalline base area is provided and a base-connecting area of the second conductivity type is provided above the base area. An insulating area is provided above the base-connecting area and a window is formed in the insulating area and the base-connecting area so as to at least partly expose the base area. An insulating sidewall spacer is provided in the window in order to insulate the base-connecting area. An emitter layer which forms a monocrystalline emitter area above the base area and a polycrystalline emitter area above the insulating area and the sidewall spacer is differentially deposited and structured, and a tempering step is carried out.
    Type: Application
    Filed: June 15, 2005
    Publication date: October 20, 2005
    Inventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
  • Publication number: 20040185611
    Abstract: The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate. The method comprises generating an MOS preparation structure in the MOS area, wherein the MOS preparation structure comprises an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer. Further, a bipolar preparation structure is generated in the bipolar area, which comprises a conductive layer and a mask layer on the conductive layer. The mask layer is thinned in the area of the gate electrode. For determining a gate electrode and a base terminal area, common structuring of the gate electrode layer and the conductive layer is performed.
    Type: Application
    Filed: February 6, 2004
    Publication date: September 23, 2004
    Applicant: Infineon Technologies AG
    Inventors: Adrian Berthold, Josef Bock, Jurgen Holz, Wolfgang Klein
  • Publication number: 20020168829
    Abstract: The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.
    Type: Application
    Filed: June 3, 2002
    Publication date: November 14, 2002
    Inventors: Josef Bock, Wolfgang Klein, Herbert Schafer, Martin Franosch, Thomas Meister, Reinhard Stengl
  • Publication number: 20020132440
    Abstract: During the production of integrated semiconductor structures, it is often necessary to differently dope immediately adjacent regions. A method is provided for producing two adjacent regions of a predetermined area in an integrated semiconductor, whereby a first region of the two adjacent regions includes a doping with a lower target concentration than a second region. The predetermined area of a semiconductor blank is doped with a dopant until a concentration of the dopant is obtained that is at least as high as the target concentration of the second region. A protective layer is applied to the second region, and the dopant is out-diffused from the first region until a concentration of dopant is obtained that corresponds to the target concentration of the first region.
    Type: Application
    Filed: January 22, 2002
    Publication date: September 19, 2002
    Inventor: Josef Bock
  • Patent number: 4927479
    Abstract: The plant comprises a first vacuum plate with openings on which a sheet may be fixed in an exact planar way by suction. A second plate with a slightly arcuated surface and turned towards the first plate is adjustable in height by two compressing cylinders and is pivotingly fixed to the structure. The second plate is also a vacuum plate and may be unrolled on the first plate. During the unrolling motion, the second plate is conducted by means of retractable bolts which are engaged into corresponding openings of the first plate. To compress two sheets, a first sheet is fixed in an exact planar way to the first plate by suction and transferred by an unrolling motion of the second plate thereon, the suction force of the plate being reduced and that of the second plate being correspondingly increased. A second sheet is then fixed to the first plate and cold- or hot-compressed according to the same unrolling process as the first sheet.
    Type: Grant
    Filed: February 28, 1989
    Date of Patent: May 22, 1990
    Inventor: Josef Bock