Patents by Inventor Josef Bock
Josef Bock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120074405Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.Type: ApplicationFiled: December 8, 2011Publication date: March 29, 2012Applicant: Infineon Technologies AGInventors: Herbert Schäfer, Martin Franosch, Thomas Meister, Josef Böck
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Patent number: 8102052Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.Type: GrantFiled: February 14, 2011Date of Patent: January 24, 2012Assignee: Infineon Technologies AGInventors: Herbert Schäfer, Martin Franosch, Thomas Meister, Josef Böck
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Patent number: 8003475Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.Type: GrantFiled: March 20, 2008Date of Patent: August 23, 2011Assignee: Infineon Technologies AGInventors: Josef Böck, Rudolf Lachner, Thomas Meister, Reinhard Stengl, Herbert Schäfer, Martin Seck
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Patent number: 7968972Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.Type: GrantFiled: March 3, 2010Date of Patent: June 28, 2011Assignee: Infineon Technologies AGInventors: Josef Böck, Thomas Meister, Reinhard Stengl, Herbert Schäfer
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Publication number: 20110133188Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.Type: ApplicationFiled: February 14, 2011Publication date: June 9, 2011Applicant: Infineon Technologies AGInventors: Herbert Schäfer, Martin Franosch, Thomas Meister, Josef Böck
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Patent number: 7947552Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.Type: GrantFiled: April 21, 2008Date of Patent: May 24, 2011Assignee: Infineon Technologies AGInventors: Herbert Schäfer, Martin Franosch, Thomas Meister, Josef Böck
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Patent number: 7873433Abstract: This invention relates to a system and a method for optimization of the process performance of a web-processing machine, in particular a machine for the production or further processing of paper, paperboard or tissue, including the following steps: storage of specific data of a component on a data storage unit fitted to the component; and/or measurement of relevant properties of the component by way of a sensor unit fitted to the component; sending of the specific data and/or the measured relevant properties to an open-loop control unit and/or a closed-loop control unit; and optimization of the process performance by way of the open-loop control unit and/or the closed-loop control unit using specific data and/or the measured properties of the component.Type: GrantFiled: November 16, 2006Date of Patent: January 18, 2011Assignee: Voith Patent GmbHInventors: Karl Josef Böck, Herbert Schrefl, Peter Putschögl, Georg Gobec, Norbert Gamsjäger
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Publication number: 20100155896Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.Type: ApplicationFiled: March 3, 2010Publication date: June 24, 2010Inventors: Josef Böck, Thomas Meister, Reinhard Stengl, Herbert Schafer
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Patent number: 7719088Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.Type: GrantFiled: October 20, 2005Date of Patent: May 18, 2010Assignee: Infineon Technologies AGInventors: Josef Böck, Thomas Meister, Reinhard Stengl, Herbert Schäfer
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Patent number: 7497399Abstract: Process and apparatus for winding a material web onto a reel spool to produce a wound reel. The process is performed in the apparatus and includes producing the material web, online smoothing of the produced material web, guiding the smoothed material web over a reel drum and through a nip formed between the reel drum and one of the reel spool and the wound reel, maintaining contact between the reel drum and the one of the reel spool and the wound reel, and reeling the smoothed material web while transversely moving at least one of the reel drum and the one of the reel spool and the wound reel relative to a web travel direction. The instant abstract is neither intended to define the invention disclosed in this specification nor intended to limit the scope of the invention in any way.Type: GrantFiled: December 2, 2002Date of Patent: March 3, 2009Assignee: Voith Sulzer Papiertechnik Patent GmbHInventor: Karl Josef Böck
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Patent number: 7449389Abstract: A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.Type: GrantFiled: October 27, 2006Date of Patent: November 11, 2008Assignee: Infineon Technologies AGInventors: Thomas Meister, Herbert Schäfer, Josef Böck, Rudolf Lachner
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Publication number: 20080227261Abstract: The invention relates to a method for fabricating a transistor structure, comprising at least a first and a second bipolar transistor having different collector widths. The invention is distinguished by the fact that all junctions between differently doped regions have a sharp interface. In this case, by way of example, a first collector region 2.1 is suitable for a high-frequency transistor with high limiting frequencies fT and a second collector region 2.2 is suitable for a high-voltage transistor with increased breakdown voltages.Type: ApplicationFiled: March 20, 2008Publication date: September 18, 2008Inventors: Josef Bock, Rudolf Lachner, Thomas Meister, Reinhard Stengl, Herbert Schafer, Martin Seck
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Patent number: 7420228Abstract: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region, and an emitter region of the first conduction type which is provided above the base region on the side remote from the collection region. A carbon-doped semiconductor region is provided on the first side alongside the collector region. The bipolar transistor is characterized in that the carbon-doped semiconductor region has a carbon concentration of 1019-1021 cm?3 and the base region has a smaller cross section than the collector region and the collector region has, in the overlap region with the base region, a region having an increased doping compared with the remaining region.Type: GrantFiled: October 7, 2005Date of Patent: September 2, 2008Assignee: Infineon Technologies AGInventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
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Patent number: 7371650Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.Type: GrantFiled: October 24, 2003Date of Patent: May 13, 2008Assignee: Infineon Technologies AGInventors: Josef Böck, Rudolf Lachner, Thomas Meister, Reinhard Stengl, Herbert Schäfer, Martin Seck
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Publication number: 20080102593Abstract: A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.Type: ApplicationFiled: October 27, 2006Publication date: May 1, 2008Applicant: INFINEON TECHNOLOGIES AGInventors: Thomas Meister, Herbert Schafer, Josef Bock, Rudolf Lachner
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Patent number: 7285470Abstract: The invention relates to a method for producing a bipolar semiconductor element, especially a bipolar transistor, and a corresponding bipolar semiconductor component.Type: GrantFiled: September 30, 2005Date of Patent: October 23, 2007Assignee: Infineon Technologies AGInventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
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Patent number: 7256472Abstract: A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance.Type: GrantFiled: July 11, 2003Date of Patent: August 14, 2007Assignee: Infineon Technologies AGInventors: Josef Bock, Thomas Meister, Andriy Romanyuk, Herbert Schäfer
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Patent number: 7105415Abstract: The invention relates to a method for producing a bipolar transistor. A semiconductor substrate is provided that encompasses a collector area of a first conductivity type, which is embedded therein and is bare towards the top. A monocrystalline base area is provided and a base-connecting area of the second conductivity type is provided above the base area. An insulating area is provided above the base-connecting area and a window is formed in the insulating area and the base-connecting area so as to at least partly expose the base area. An insulating sidewall spacer is provided in the window in order to insulate the base-connecting area. An emitter layer which forms a monocrystalline emitter area above the base area and a polycrystalline emitter area above the insulating area and the sidewall spacer is differentially deposited and structured, and a tempering step is carried out.Type: GrantFiled: June 15, 2005Date of Patent: September 12, 2006Assignee: Infineon Technologies AGInventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
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Publication number: 20060097352Abstract: A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance.Type: ApplicationFiled: July 11, 2003Publication date: May 11, 2006Inventors: Josef Bock, Thomas Meister, Andriy Romanyuk, Herbert Schafer
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Patent number: 7018884Abstract: The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate. The method comprises generating an MOS preparation structure in the MOS area, wherein the MOS preparation structure comprises an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer. Further, a bipolar preparation structure is generated in the bipolar area, which comprises a conductive layer and a mask layer on the conductive layer. The mask layer is thinned in the area of the gate electrode. For determining a gate electrode and a base terminal area, common structuring of the gate electrode layer and the conductive layer is performed.Type: GrantFiled: February 6, 2004Date of Patent: March 28, 2006Assignee: Infineon Technologies AGInventors: Adrian Berthold, Josef Böck, Jürgen Holz, Wolfgang Klein