Patents by Inventor Josef Czeslaw Mitros

Josef Czeslaw Mitros has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device with reduced cell size
    Patent number: 6958269
    Abstract: A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: October 25, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Josef Czeslaw Mitros, Imran Khan, Lily Springer
  • Memory device with reduced cell size
    Publication number: 20030235949
    Abstract: A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.
    Type: Application
    Filed: June 24, 2002
    Publication date: December 25, 2003
    Applicant: Texas Instruments Incorporated
    Inventors: Josef Czeslaw Mitros, Imran Khan, Lily Springer