Abstract: An RF or other high frequency transceiver including a loopback reference channel for measurement of an absolute power level. A transmit channel in the transceiver includes a programmable power amplifier that can be controlled to operate at a selected power level, and a receive channel including a receive amplifier, mixers, filters, and analog-to-digital converters. The loopback reference channel includes a self-biased amplifier, followed by a series of buffers that generate a square wave from the received signal, and an attenuator applying an attenuation gain to the square wave. The transmit power at a programmed power level can be calculated from ratios of a measured power level of a transmitted signal as received by the receive channel to the measured power level of the transmitted signal using the loopback reference channel.

Abstract: An RF or other high frequency transceiver including a loopback reference channel for measurement of an absolute power level. A transmit channel in the transceiver includes a programmable power amplifier that can be controlled to operate at a selected power level, and a receive channel including a receive amplifier, mixers, filters, and analog-to-digital converters. The loopback reference channel includes a self-biased amplifier, followed by a series of buffers that generate a square wave from the received signal, and an attenuator applying an attenuation gain to the square wave. The transmit power at a programmed power level can be calculated from ratios of a measured power level of a transmitted signal as received by the receive channel to the measured power level of the transmitted signal using the loopback reference channel.

Abstract: A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to operate in a single ended mode and in a differential mode. Two interface pins are provided for coupling the transceiver to an antenna via a matching network, wherein the two interface pins are shareably coupled to the transmitter and to the receiver. A tunable capacitor is coupled to differential signal lines of the configurable portion, wherein the tunable capacitor is configured to be tuned to optimize impedance matching of the configurable portion for each mode of operation.

Abstract: A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer is coupled to and shared between the transmitter and the receiver. A resonator is formed by the combination of the transformer and capacitive elements of the transmitter and receiver.

Abstract: A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer is coupled to and shared between the transmitter and the receiver. A resonator is formed by the combination of the transformer and capacitive elements of the transmitter and receiver.

Abstract: A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer is coupled to and shared between the transmitter and the receiver. A resonator is formed by the combination of the transformer and capacitive elements of the transmitter and receiver.

Abstract: A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer is coupled to and shared between the transmitter and the receiver. A resonator is formed by the combination of the transformer and capacitive elements of the transmitter and receiver.

Abstract: A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to operate in a single ended mode and in a differential mode. Two interface pins are provided for coupling the transceiver to an antenna via a matching network, wherein the two interface pins are shareably coupled to the transmitter and to the receiver. A tunable capacitor is coupled to differential signal lines of the configurable portion, wherein the tunable capacitor is configured to be tuned to optimize impedance matching of the configurable portion for each mode of operation.

Abstract: A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer is coupled to and shared between the transmitter and the receiver. A resonator is formed by the combination of the transformer and capacitive elements of the transmitter and receiver.

Abstract: A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to operate in a single ended mode and in a differential mode. Two interface pins are provided for coupling the transceiver to an antenna via a matching network, wherein the two interface pins are shareably coupled to the transmitter and to the receiver. A tunable capacitor is coupled to differential signal lines of the configurable portion, wherein the tunable capacitor is configured to be tuned to optimize impedance matching of the configurable portion for each mode of operation.

Abstract: A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer is coupled to and shared between the transmitter and the receiver. A resonator is formed by the combination of the transformer and capacitive elements of the transmitter and receiver.

Abstract: A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to operate in a single ended mode and in a differential mode. Two interface pins are provided for coupling the transceiver to an antenna via a matching network, wherein the two interface pins are shareably coupled to the transmitter and to the receiver. A tunable capacitor is coupled to differential signal lines of the configurable portion, wherein the tunable capacitor is configured to be tuned to optimize impedance matching of the configurable portion for each mode of operation.

Abstract: A planar inductance, such as for monolithic HF oscillators, has planar spiral windings, each with two loops, where each winding is in the form of an “eight” with cross-conductors carrying current in the same direction and running between two loops.

Abstract: A planar inductance, in particular for monolithic HF oscillators, with planar spiral windings, wherein each winding (1) is in the form of an “eight” with three cross-conductors (6, 7, 8) carrying current in the same direction and running between two loops (1a, 1b).

Abstract: A telecommunication terminal has a voltage controller (8) which controller forms at least part of an integrated circuit (1) and includes a differential amplifier (14) having a first input (+) for receiving a reference voltage (UREF), means (16, 20) for applying a load current (22) that is provided with at least one phase shifting component (23) as a function of an output voltage of the differential amplifier (14), and a feedback path for feeding back a voltage drop at the load (22) to the second (-) of the two inputs of the differential amplifier. To provide a maximum suppression of disturbances of the output voltage over a wide frequency range and guarantee the stability of the voltage controller, the phase shifting component (23) is arranged outside the integrated circuit (1) and a plurality of separate pins (4, 5) of the integrated circuit (1) are provided for coupling the phase shifting component (23) to the output of the means (16, 20) for producing a load current and to the feedback path.

Abstract: A power MOSFET composed of a plurality of individual MOSFETs connected in parallel, wherein an additional sensing MOSFET monitors the current in the power MOSFET. The sensing MOSFET has a surface comparatively smaller than the power MOSFET and is connected in parallel with the power MOSFET with a resistor between the source of the power MOSFET and the source of the sensing MOSFET. The sensing MOSFET and resistor are integrated with an integrated circuit provided for the control of the power MOSFET.

Abstract: A semiconductor component with a power MOSFET and control circuit for controlling the power MOSFET. Both the power MOSFET and the control circuit have separate semiconductor bodies. The semiconductor body of the control circuit is arranged on one of the main surfaces of the semiconductor body of the power MOSFET. The control circuit is electrically insulated from the MOSFET by an insulating layer and mechanically coupled to the MOSFET by means of a bonding layer. The MOSFET is fastened to a cooling body which serves as a heat sink for the semiconductor component. The terminals of the control circuit and the MOSFET are attached to housing connections with leads.

Abstract: A signal voltage (E) based upon a supply voltage must be converted to a signal voltage (A) with ground reference so as to enable further processing in a logic circuit. A simple level converter comprises a series connection of a MOSFET (T1) connected to the supply voltage; the MOSFET also comprises a resistor (T2). The source terminal of the MOSFET (T1) is located at the potential of the supply voltage. The voltage to be converted is applied between the gate terminal and the source terminal, and the converted voltage occurs at the resistor (T2). The two voltages are each limited by one Zener diode (D2, D1).

Abstract: The temperature of the power semiconductor component is sensed by a bipolar transistor. The bipolar transistor is in series with a depletion mode MOSFET whose gate and source electrodes are connected together. The drain electrode is also connected to a threshold element. Normally, the FET has low impedance, so that at the input of the threshold element source potential, e.g. ground potential, is present. With current rising as a function of temperature, the current through the FET is limited to a constant, essentially temperature-independent value, and the potential at the input of the threshold element rises steeply. This condition is detected as an overtemperature signal.

Abstract: The voltage peaks occuring upon disconnection of inductive loads are normally attenuated by a by-pass diode connected in parallel with the load. The driving countervoltage is thereby limited to the value of the forward voltage drop of the diode. For a power MOSFET with a source-side inductive load, the driving countervoltage is increased by placing a series connection of an additional MOSFET and a Zener diode between the gate of the power MOSFET and the connection of the load which is remote from the power MOSFET. The driving countervoltage at the source now becomes the Zener voltage plus the occuring gate-source voltage of the power MOSFET.