Patents by Inventor Josef Georg Bauer
Josef Georg Bauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11387359Abstract: A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 ?m. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.Type: GrantFiled: December 13, 2019Date of Patent: July 12, 2022Assignee: Infineon Technologies AGInventors: Oliver Humbel, Josef-Georg Bauer, Jens Brandenburg, Diana Car, Philipp Sebastian Koch, Angelika Koprowski, Sebastian Kremp, Thomas Kurzmann, Erwin Lercher, Holger Ruething
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Publication number: 20200357883Abstract: A power semiconductor device includes an active region having a total volume with a central volume forming at least 20% of the total volume, a peripheral volume forming at least 20% of the total volume and surrounding the central volume, and an outermost peripheral volume forming at least 5% of the total volume and surrounding the peripheral volume. The peripheral volume has a constant lateral distance from an edge termination region. A first doped semiconductor region is electrically connected with a first load terminal at a semiconductor body frontside. A second doped semiconductor region is electrically connected with a second load terminal at a semiconductor body backside. The first and/or second doped semiconductor region has: a central portion extending into the central volume and having a central average dopant dose; and a peripheral portion extending into the peripheral volume and having a peripheral average dopant dose.Type: ApplicationFiled: May 6, 2020Publication date: November 12, 2020Inventors: Manfred Pfaffenlehner, Josef-Georg Bauer, Frank Dieter Pfirsch, Thilo Scheiper, Konrad Schraml
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Publication number: 20200194585Abstract: A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 ?m. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.Type: ApplicationFiled: December 13, 2019Publication date: June 18, 2020Inventors: Oliver Humbel, Josef-Georg Bauer, Jens Brandenburg, Diana Car, Philipp Sebastian Koch, Angelika Koprowski, Sebastian Kremp, Thomas Kurzmann, Erwin Lercher, Holger Ruething
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Patent number: 10388722Abstract: A power semiconductor device is disclosed. In one example, the device comprises: a semiconductor body comprising a drift region, the drift region having dopants of a first conductivity type; an active region having at least one power cell; least partially into the semiconductor body; the at least one power cell being configured to conduct a load current between said terminals and to block a blocking voltage applied between said terminals; an edge that laterally terminates the semiconductor body; and a non-active termination structure arranged in between the edge and the active region. The termination structure comprises: at least one doped semiconductor region implemented in the semiconductor body; a conductor structure, and an ohmic path that electrically couples the conductor structure with an electrical potential of the first load terminal.Type: GrantFiled: October 12, 2017Date of Patent: August 20, 2019Assignee: Infineon Technologies AGInventors: Elmar Falck, Josef-Georg Bauer, Jens Brandenburg, Hans-Joachim Schulze
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Publication number: 20180114841Abstract: A power semiconductor device is disclosed. In one example, the device comprises: a semiconductor body comprising a drift region, the drift region having dopants of a first conductivity type; an active region having at least one power cell; least partially into the semiconductor body; the at least one power cell being configured to conduct a load current between said terminals and to block a blocking voltage applied between said terminals; an edge that laterally terminates the semiconductor body; and a non-active termination structure arranged in between the edge and the active region. The termination structure comprises: at least one doped semiconductor region implemented in the semiconductor body; a conductor structure, and an ohmic path that electrically couples the conductor structure with an electrical potential of the first load terminal.Type: ApplicationFiled: October 12, 2017Publication date: April 26, 2018Applicant: Infineon Technologies AGInventors: Elmar Falck, Josef-Georg Bauer, Jens Brandenburg, Hans-Joachim Schulze
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Patent number: 9859395Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.Type: GrantFiled: September 30, 2014Date of Patent: January 2, 2018Assignee: Infineon Technologies AGInventors: Gerhard Schmidt, Josef-Georg Bauer, Carsten Schaeffer, Oliver Humbel, Angelika Koprowski, Sirinpa Monayakul
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Patent number: 9484221Abstract: A power semiconductor device has a semiconductor body having a first surface and a second surface that runs substantially parallel to the first surface. A first metallization is arranged on the first surface. A second metallization is arranged on the second surface. The semiconductor body includes an n-doped first semiconductor region spaced apart from the first metallization and having a first maximum doping concentration, an n-doped second semiconductor region having a second maximum doping concentration higher than the first maximum doping concentration and adjoining the first semiconductor region, and a third semiconductor region in ohmic contact with the second metallization, arranged between the second metallization and the second semiconductor region, and adjoining the second semiconductor region. The second semiconductor region is made of a semiconductor material which includes electrically active chalcogen impurities as donors.Type: GrantFiled: January 13, 2014Date of Patent: November 1, 2016Assignee: Infineon Technologies AGInventors: Gerhard Schmidt, Josef Georg Bauer
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Patent number: 9349799Abstract: Disclosed are a method and a semiconductor device. The method includes implanting recombination center atoms via a first surface into a semiconductor body, and causing the implanted recombination center atoms to diffuse in the semiconductor body in a first diffusion process.Type: GrantFiled: August 13, 2015Date of Patent: May 24, 2016Assignee: Infineon Technologies AGInventors: Gerhard Schmidt, Josef Georg Bauer, Mario Barusic, Oliver Humbel, Hans Millonig, Werner Schustereder
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Publication number: 20160049474Abstract: Disclosed are a method and a semiconductor device. The method includes implanting recombination center atoms via a first surface into a semiconductor body, and causing the implanted recombination center atoms to diffuse in the semiconductor body in a first diffusion process.Type: ApplicationFiled: August 13, 2015Publication date: February 18, 2016Inventors: Gerhard Schmidt, Josef Georg Bauer, Mario Barusic, Oliver Humbel, Hans Millonig, Werner Schustereder
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Patent number: 9263529Abstract: Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.Type: GrantFiled: March 21, 2015Date of Patent: February 16, 2016Assignee: Infineon Technologies Austria AGInventors: Gerhard Schmidt, Josef-Georg Bauer
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Patent number: 9209027Abstract: A method includes implanting recombination center atoms via a first surface into a semiconductor body and causing the implanted recombination center atoms to diffuse in the semiconductor body in a first diffusion process.Type: GrantFiled: August 14, 2014Date of Patent: December 8, 2015Assignee: Infineon Technologies AGInventors: Gerhard Schmidt, Josef Georg Bauer
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Publication number: 20150200247Abstract: A power semiconductor device has a semiconductor body having a first surface and a second surface that runs substantially parallel to the first surface. A first metallization is arranged on the first surface. A second metallization is arranged on the second surface. The semiconductor body includes an n-doped first semiconductor region spaced apart from the first metallization and having a first maximum doping concentration, an n-doped second semiconductor region having a second maximum doping concentration higher than the first maximum doping concentration and adjoining the first semiconductor region, and a third semiconductor region in ohmic contact with the second metallization, arranged between the second metallization and the second semiconductor region, and adjoining the second semiconductor region. The second semiconductor region is made of a semiconductor material which includes electrically active chalcogen impurities as donors.Type: ApplicationFiled: January 13, 2014Publication date: July 16, 2015Inventors: Gerhard Schmidt, Josef Georg Bauer
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Publication number: 20150194491Abstract: Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.Type: ApplicationFiled: March 21, 2015Publication date: July 9, 2015Inventors: Gerhard Schmidt, Josef-Georg Bauer
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Publication number: 20150056788Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.Type: ApplicationFiled: September 30, 2014Publication date: February 26, 2015Inventors: Gerhard Schmidt, Josef-Georg Bauer, Carsten Schaeffer, Oliver Humbel, Angelika Koprowski, Sirinpa Monayakul
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Patent number: 8884342Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.Type: GrantFiled: August 29, 2012Date of Patent: November 11, 2014Assignee: Infineon Technologies AGInventors: Gerhard Schmidt, Josef-Georg Bauer, Carsten Schaeffer, Oliver Humbel, Angelika Koprowski, Sirinpa Monayakul
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Publication number: 20140061733Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.Type: ApplicationFiled: August 29, 2012Publication date: March 6, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Gerhard Schmidt, Josef-Georg Bauer, Carsten Schaeffer, Oliver Humbel, Angelika Koprowski, Sirinpa Monayakul
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Patent number: 7612388Abstract: The power semiconductor element has an emitter region and a stop zone in front of the emitter region. The conductivities of the emitter region and of the stop zone are opposed to one another. In order to reduce not only the static but also the dynamic loss of the power semiconductor foreign atoms are used in the stop-zone. The foreign atoms have at least one energy level within the band gap of the semiconductor and at least 200 meV away from the conduction band and valence band of the semiconductor.Type: GrantFiled: January 17, 2001Date of Patent: November 3, 2009Assignee: Infineon Technologies AGInventors: Josef-Georg Bauer, Heinrich Brunner, Hans-Joachim Schulze
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Patent number: 7233031Abstract: A vertical power semiconductor component, e.g. a diode or an IGBT, in which there are formed, on the rear side of a substrate, a rear side emitter or a cathode emitter and, over that, a rear side metal layer that at least partly covers the latter, is defined by the fact that, in the edge region of the component, provision is made of injection attenuation means for reducing the charge carrier injection from the rear side emitter or the cathode emitter into said edge section.Type: GrantFiled: July 7, 2004Date of Patent: June 19, 2007Assignee: Infineon Technologies AGInventors: Anton Mauder, Holger RĂ¼thing, Gerhard Miller, Hans Joachim Schulze, Josef Georg Bauer, Elmar Falck
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Publication number: 20050035405Abstract: A vertical power semiconductor component, e.g. a diode or an IGBT, in which there are formed, on the rear side (R) of a substrate (S), a rear side emitter (14, 14a) or a cathode emitter (24) and, over that, a rear side metal layer (15; 25) that at least partly covers the latter, is defined by the fact that, in the edge region (11; 21) of the component (1-4), provision is made of injection attenuation means (18; 28; 14a; 15a) for reducing the charge carrier injection from the rear side emitter (14, 14a) or the cathode emitter (24) into said edge section (11; 21).Type: ApplicationFiled: July 7, 2004Publication date: February 17, 2005Applicant: Infineon Technologies AGInventors: Anton Mauder, Holger Ruthing, Gerhard Miller, Hans Schulze, Josef Georg Bauer, Elmar Falck
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Publication number: 20010005024Abstract: The power semiconductor element has an emitter region and a stop zone in front of the emitter region. The conductivities of the emitter region and of the stop zone are opposed to one another. In order to reduce not only the static but also the dynamic loss of the power semiconductor foreign atoms are used in the stop-zone. The foreign atoms have at least one energy level within the band gap of the semiconductor and at least 200 meV away from the conduction band and valence band of the semiconductor.Type: ApplicationFiled: January 17, 2001Publication date: June 28, 2001Inventors: Josef-Georg Bauer, Heinrich Brunner, Hans-Joachim Schulze