Abstract: An integrated logic circuit comprises a memory area, wherein the memory area comprises a plurality of groups of memory cells, each group of memory cells assigned an address. The memory area further comprises an address decoder having a plurality of address inputs for receiving an address and for selecting a group of memory cells to which the received address is assigned and a plurality of data outputs for outputting information stored in a group of memory cells which is selected by the address decoder. The integrated logic circuit further comprises a coupling device which couples at least one portion of the data outputs of the memory area to at least one portion of the address inputs of the address decoder.

Abstract: A device and a method including current measurement and/or amplification is disclosed. One embodiment provides supplying a current to be measured to a current amplifier. The current is amplified by the current amplifier. The amplified current or a current generated is fed back therefrom to the current amplifier. The current amplifier may include a current mirror. Furthermore, at least one delay means may be used by which the process of current amplification and/or current feedback may be delayed correspondingly.

Abstract: An integrated logic circuit comprises a memory area, wherein the memory area comprises a plurality of groups of memory cells, each group of memory cells assigned an address. The memory area further comprises an address decoder having a plurality of address inputs for receiving an address and for selecting a group of memory cells to which the received address is assigned and a plurality of data outputs for outputting information stored in a group of memory cells which is selected by the address decoder. The integrated logic circuit further comprises a coupling device which couples at least one portion of the data outputs of the memory area to at least one portion of the address inputs of the address decoder.

Abstract: For synchronising the data transmission between a CMOS circuit (1) and a bipolar circuit (2) a DLL (delayed lock loop) is provided which sets a phase deviation between the operating clocks (CLK1, CLK2) of the two circuits (1, 2), and changes the phase of at least one of the two clocks (CLK1, CLK2) according to this phase deviation, until the two clocks are in phase, in such a way that the data (DATA1) provided by the first circuit (1) can then be taken on by the second circuit (2). To this end, the DLL circuit comprises a phase detector (6), a loop filter (7) and an adjustable element (8).

Abstract: A device and a method including current measurement and/or amplification is disclosed. One embodiment provides supplying a current to be measured to a current amplifier. The current is amplified by the current amplifier. The amplified current or a current generated is fed back therefrom to the current amplifier. The current amplifier may include a current mirror. Furthermore, at least one delay means may be used by which the process of current amplification and/or current feedback may be delayed correspondingly.

Abstract: A system and a method for determining frequencies is disclosed. In one embodiment, the system includes a delay device to generate a delayed second signal from a first signal. A logic device generates a third signal from the first signal and the second signal. A device filters a DC component from the third signal. A device determines the frequency of the first signal based on the DC component.

Abstract: An output signal is generated with a predetermined phase shift with respect to an input signal using a closed loop control. The input and output signal of the closed loop control are logically combined in accordance with first and second combinatory logic to generate first and second control signals. The first and second control signals selectively activate first and second current sources, respectively. The current supplied by the first current source charges a capacitance controlling the closed loop control, while the current supplied by the second current source discharges the capacitance. By selecting the types of the combinatory logics as well as the ratio of the currents supplied by the first and second current sources, the phase shift of the output signal with respect to the input signal can be variably adapted to individual requirements.

Abstract: In a circuit arrangement for transmitting impulses via a transmission path which allows short pulses to be transmitted via a longer transmission path, for example within integrated circuits, a frequency divider is provided having an input at which the pulses to be transmitted are present and an output connected to the transmission path. Further, a frequency multiplier is provided, whose input is connected to the transmission path and having an output at which the transmitted impulses are present.

Abstract: The novel frequency divider has an adjustable divider ratio. Such circuits are subject to demands for ever higher clock frequencies. The circuit generates the output signal in a blockwise manner and converts it into a sequential signal in a parallel-serial converter on the output side and outputs it in a bitwise manner. As a result, the essential part of the frequency divider circuit can be operated with a slower frequency than the input frequency, which in turn enables higher input frequencies.

Abstract: A circuit arrangement generates a resistance behavior with an adjustable positive temperature coefficient. A second ohmic resistance element is connected in parallel with a series circuit of a first ohmic resistance element and a diode element wherein the value of the second ohmic resistance element is set corresponding to the desired temperature coefficient.

Abstract: Circuit arrangement for generating a bias potential includes a first transistor connected on a collector side thereof to a supply potential, a first resistor connected between a base and the collector of the first transistor, a first current source connected between the base of the first transistor and a reference potential, a second current source connected between an emitter of the first transistor and the reference potential, a second transistor connected on a collector side thereof to the supply potential and on a base side thereof to the emitter of the first transistor, a third current source connected between the emitter of the second transistor and the reference potential, a third transistor carrying the bias potential on a collector side thereof, a second resistor connected between the emitter of the second transistor and a base of the third transistor, a third resistor connected between the collector of the third transistor and the supply potential, a first diode connected in the forward direction th

Abstract: A digital switching stage includes a differential amplifier having a first and a second differential amplifier branch. A first resistor is connected in the first differential amplifier branch and has a first terminal and a second terminal. The first terminal is a terminal for a first supply potential. A first bipolar transistor is connected in an emitter follower circuit with respect to the second terminal of the first resistor and has an emitter being connected to an output terminal. A second bipolar transistor has a base and has a collector-to-emitter path being connected between the output terminal and a terminal for a second supply potential. A second resistor is connected in the second differential amplifier branch and has a first terminal and a second terminal. The first terminal of the second resistor is connected to the output terminal and the second terminal of the second resistor is connected to the base of the second bipolar transistor.

Abstract: A synchronized, digital sequential circuit includes state-controlled memory elements, each having a clock input, at least two outputs being complementary to one another and at least two inputs, which are connected to a logical OR linkage or wired OR connection. At least two state-controlled memory elements are connected in series. A first memory element performs the OR linkage or operation and a second memory element performs the AND linkage or operation of a combinatorial logic function. The settling time of a memory element and the delay time for forming the OR and AND linkages or operations coincide. Therefore, a high speed of operation is possible in the sequential circuit.

Abstract: An electronic pulse counter includes a given number of shift registers each having a different number of memory elements, an input, an output and a clocking line. Each of the shift registers is countercoupled by a negation between the input and the output thereof. A pulse counter input is formed by interconnection of the clocking lines of all of the shift registers. Pulse counter outputs are formed by the outputs of the shift registers.