Patents by Inventor Josef Hoglauer

Josef Hoglauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250218914
    Abstract: A package is disclosed. In one example, the package includes an at least partially electrically conductive carrier having a coupling structure and a reference potential structure which is electrically decoupled from the coupling structure and which is configured to be brought to an electric reference potential during operation of the package, an intermediate structure at the carrier and having an electrically insulating structure oriented towards the carrier and having a mounting structure facing away from the carrier. An electronic component is mounted on the mounting structure and being electrically coupled with the coupling structure. An encapsulant is encapsulating at least part of the intermediate structure, at least part of the electronic component, and part of the carrier so as to expose at least part of the reference potential structure and at least part of the coupling structure.
    Type: Application
    Filed: December 11, 2024
    Publication date: July 3, 2025
    Applicant: Infineon Technologies AG
    Inventors: Hao ZHUANG, Josef HÖGLAUER, Milad MOSTOFIZADEH, Markus DINKEL, Angela KESSLER
  • Publication number: 20250198686
    Abstract: A system includes: an ion trap device; an application board; a base plate arranged on the application board and having one or more through-holes; a substrate having a first side and a second side, the ion trap device being arranged on the first side and the second side being arranged on the base plate; electronic circuitry and/or electrical components arranged on the application board and configured to generate one or more signals for the ion trap device; and one or more conductive traces arranged on the application board and electrically coupled to the electronic circuitry and/or electrical components. The one or more conductive traces are routed to the base plate. An electrical connection is formed between the one or more conductive traces and the second side of the substrate via the one or more through-holes of the base plate.
    Type: Application
    Filed: February 26, 2025
    Publication date: June 19, 2025
    Inventors: Günther Lohmann, Ralf Otremba, Josef Höglauer, Clemens Rössler, Silke Katharina Auchter
  • Publication number: 20250157895
    Abstract: A semiconductor chip package includes a semiconductor chip having a first side and a second side opposite the first side. The first side includes chip pads. The semiconductor chip package also includes a first leadframe structured to form a footprint of the semiconductor chip package. The semiconductor chip package further includes a structured metal plate disposed between the first leadframe and the semiconductor chip. The first side of the semiconductor chip faces the structured metal plate. A pattern of bond material is disposed between the first leadframe and the structured metal plate. The pattern of bond material is configured to electrically and mechanically connect structures of the first leadframe to structures of the structured metal plate. The semiconductor chip package also includes a mold compound embedding the first leadframe, the structured metal plate and the semiconductor chip.
    Type: Application
    Filed: November 12, 2024
    Publication date: May 15, 2025
    Inventors: Hao Zhuang, Milad Mostofizadeh, Josef Höglauer, Ralf Otremba, MargieTumulak Rios
  • Patent number: 12264867
    Abstract: A cryostat socket for holding an ion trap device mounted on a substrate in a cryostat includes a housing frame provided for pre-assembly in the cryostat. A pin insert is arranged in the housing frame. The pin insert includes a base plate and contact pins. The contact pins are arranged in an array. A housing cover has a receptacle for the substrate. The housing cover, when assembled with the housing frame, exerts a compressive force on a front side of the substrate by which a rear side of the substrate is pressed onto the contact pins.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: April 1, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Günther Lohmann, Ralf Otremba, Josef Höglauer, Clemens Rössler, Silke Katharina Auchter
  • Publication number: 20240030200
    Abstract: In an embodiment, a semiconductor package includes a lower surface having a low voltage contact pad, a high voltage contact pad, an output contact pad, and at least one control contact pad. The semiconductor package further includes a half-bridge circuit including a first transistor device having a first major surface and a second transistor device having a first major surface, the first and second transistor devices being electrically coupled in series at an output node, and a control device that is electrically coupled to the first transistor device and the second transistor device. The first major surface of the first transistor device and of the second transistor device are arranged substantially perpendicularly to the lower surface of the semiconductor package.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 25, 2024
    Inventors: Christian Irrgang, Thomas Behrens, Ludwig Heitzer, Josef Hoglauer, Thorsten Meyer, Thorsten Scharf, Frank Zudock
  • Publication number: 20240030111
    Abstract: A semiconductor package includes low voltage and high voltage contact pads, an output contact pad, a half-bridge circuit, and first, second and third leads. The half bridge circuit includes first and second transistor devices coupled in series at an output node. Both transistor devices have a first major surface which extends substantially perpendicularly to the low voltage contact pad, the high voltage contact pad, and the output contact pad. Both transistor devices are arranged in a device portion of the package and are mounted on a first lead, the first lead providing the output contact pad and being arranged on a first side of the device portion. The second and third leads are arranged in a common plane on a second side of the device portion that opposes the first side. The second lead provides the low voltage pad and the third second lead provides the high voltage output pad.
    Type: Application
    Filed: July 12, 2023
    Publication date: January 25, 2024
    Inventors: Sergey Yuferev, Josef Höglauer, Gerhard Thomas Nöbauer, Hao Zhuang
  • Publication number: 20230230903
    Abstract: A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.
    Type: Application
    Filed: December 21, 2022
    Publication date: July 20, 2023
    Applicant: Infineon Technologies AG
    Inventors: Hooi Boon TEOH, Hao ZHUANG, Oliver BLANK, Paul Armand CALO, Markus DINKEL, Josef Höglauer, Daniel Hölzl, Wee Aun JASON LIM, Gerhard Thomas Nöbauer, Ralf OTREMBA, Martin Pölzl, Ying Pok SAM, Xaver Schlögel, Chee Voon TAN
  • Publication number: 20230197577
    Abstract: A semiconductor device includes a premolded leadframe, including a main surface, at least one electrical contact extending out of the main surface, and an opposite main surface arranged opposite to the main surface. The semiconductor device further includes a semiconductor package arranged on the main surface and laterally displaced to the at least one electrical contact of the premolded leadframe. The semiconductor package includes a semiconductor chip and at least one electrical contact. Surfaces of the at least one electrical contact of the premolded leadframe and the at least one electrical contact of the semiconductor package facing away from the main surface are flush.
    Type: Application
    Filed: December 15, 2022
    Publication date: June 22, 2023
    Inventors: Thorsten Scharf, Josef Höglauer, Angela Kessler, Claus Waechter
  • Publication number: 20230168023
    Abstract: A cryostat socket for holding an ion trap device mounted on a substrate in a cryostat includes a housing frame provided for pre-assembly in the cryostat. A pin insert is arranged in the housing frame. The pin insert includes a base plate and contact pins. The contact pins are arranged in an array. A housing cover has a receptacle for the substrate. The housing cover, when assembled with the housing frame, exerts a compressive force on a front side of the substrate by which a rear side of the substrate is pressed onto the contact pins.
    Type: Application
    Filed: November 21, 2022
    Publication date: June 1, 2023
    Inventors: Günther Lohmann, Ralf Otremba, Josef Höglauer, Clemens Rössler, Silke Katharina Auchter
  • Patent number: 10109609
    Abstract: A connection structure is provided that includes a semiconductor substrate, a first layer arranged on the semiconductor substrate, the first layer being configured to provide shielding against radioactive rays, a second layer arranged on the first layer, the second layer including solder including Pb, and an electrically conductive member arranged on the second layer.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 23, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Patent number: 9437516
    Abstract: A semiconductor package includes a semiconductor die and a metal clip. In one embodiment, the semiconductor die is embedded in an insulating material and has a first surface facing in a first direction, a second surface facing in a second direction opposite the first direction and an edge extending between the first and second surfaces. The metal clip is embedded in the insulating material above the die and bonded to the second surface of the die. Part of the metal clip extends laterally beyond the edge of the die and vertically in the first direction to provide galvanic redistribution at the second surface of the die. Other embodiments of semiconductor packages are also provided.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: September 6, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Höglauer, Manfred Schindler, Johannes Lodermeyer, Thorsten Scharf
  • Patent number: 9312760
    Abstract: A power converter is described that includes components arranged within a first die and a second die of a single package. The first die includes one or more first switches coupled to a switching node of a power stage. The second die includes one or more second switches coupled to the switching node of the power stage, a feedback control unit configured to detect a current level at the one or more second switches of the power stage, and a controller unit configured to control the one or more first switches and the one or more second switches of the power stage based at least in part on the current level detected by the feedback control unit.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: April 12, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Christoph Sandner, Roman Riederer, Josef Höglauer, Stephan Auer
  • Patent number: 9196554
    Abstract: An electronic component includes at least one semiconductor device and a redistribution board comprising at least two nonconductive layers and a conductive redistribution structure. The semiconductor device is embedded in the redistribution board and electrically coupled to the redistribution structure and the redistribution board has a side face with a step. An outer contact pad of the redistribution structure is arranged on the step.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: November 24, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Patent number: 9196577
    Abstract: A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: November 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Patent number: 9123701
    Abstract: A semiconductor die includes a semiconductor body, a transistor device disposed in the semiconductor body and having a gate, a source and a drain, and a sense device disposed in the semiconductor body and operable to sense a parameter associated with the transistor device. The die further includes a source pad at a first side of the semiconductor body and electrically connected to the source of the transistor device, a drain pad at a second side of the semiconductor body opposing the first side and electrically connected to the drain of the transistor device, and a sense pad at the second side of the semiconductor body and spaced apart from the drain pad. The sense pad is electrically connected to the sense device. A corresponding package and method of manufacturing are also disclosed.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: September 1, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Höglauer, Gerhard Nöbauer, Martin Pölzi
  • Patent number: 9099391
    Abstract: A semiconductor package includes a base, a die attached to the base, a lead and a connector electrically connecting the lead to the die. A mold compound encapsulates the die, the connector, at least part of the base, and part of the lead, so that the lead extends outward from the mold compound. An electrical insulation layer separate from the mold compound is attached to a surface of the mold compound over the connector. The electrical insulation layer has a fixed, defined thickness so that the package has a guaranteed minimum spacing between an apex of the connector and a surface of the electrical insulation layer facing away from the connector.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 4, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Jürgen Schredl, Wolfgang Peinhopf, Fabio Brucchi, Josef Höglauer
  • Publication number: 20150200178
    Abstract: A connection structure is provided that includes a semiconductor substrate, a first layer arranged on the semiconductor substrate, the first layer being configured to provide shielding against radioactive rays, a second layer arranged on the first layer, the second layer including solder including Pb, and an electrically conductive member arranged on the second layer.
    Type: Application
    Filed: January 13, 2014
    Publication date: July 16, 2015
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Publication number: 20150194373
    Abstract: A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 9, 2015
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Publication number: 20150194362
    Abstract: A semiconductor package includes a semiconductor die and a metal clip. In one embodiment, the semiconductor die is embedded in an insulating material and has a first surface facing in a first direction, a second surface facing in a second direction opposite the first direction and an edge extending between the first and second surfaces. The metal clip is embedded in the insulating material above the die and bonded to the second surface of the die. Part of the metal clip extends laterally beyond the edge of the die and vertically in the first direction to provide galvanic redistribution at the second surface of the die. Other embodiments of semiconductor packages are also provided.
    Type: Application
    Filed: January 7, 2014
    Publication date: July 9, 2015
    Inventors: Ralf Otremba, Josef Höglauer, Manfred Schindler, Johannes Lodermeyer, Thorsten Scharf
  • Publication number: 20150171748
    Abstract: A power converter is described that includes components arranged within a first die and a second die of a single package. The first die includes one or more first switches coupled to a switching node of a power stage. The second die includes one or more second switches coupled to the switching node of the power stage, a feedback control unit configured to detect a current level at the one or more second switches of the power stage, and a controller unit configured to control the one or more first switches and the one or more second switches of the power stage based at least in part on the current level detected by the feedback control unit.
    Type: Application
    Filed: December 16, 2013
    Publication date: June 18, 2015
    Applicant: Infineon Technologies Austria AG
    Inventors: Christoph Sandner, Roman Riederer, Josef Höglauer, Stephan Auer