Abstract: For synchronising the data transmission between a CMOS circuit (1) and a bipolar circuit (2) a DLL (delayed lock loop) is provided which sets a phase deviation between the operating clocks (CLK1, CLK2) of the two circuits (1, 2), and changes the phase of at least one of the two clocks (CLK1, CLK2) according to this phase deviation, until the two clocks are in phase, in such a way that the data (DATA1) provided by the first circuit (1) can then be taken on by the second circuit (2). To this end, the DLL circuit comprises a phase detector (6), a loop filter (7) and an adjustable element (8).

Abstract: An output signal is generated with a predetermined phase shift with respect to an input signal using a closed loop control. The input and output signal of the closed loop control are logically combined in accordance with first and second combinatory logic to generate first and second control signals. The first and second control signals selectively activate first and second current sources, respectively. The current supplied by the first current source charges a capacitance controlling the closed loop control, while the current supplied by the second current source discharges the capacitance. By selecting the types of the combinatory logics as well as the ratio of the currents supplied by the first and second current sources, the phase shift of the output signal with respect to the input signal can be variably adapted to individual requirements.

Abstract: An output signal is generated with a predetermined phase shift with respect to an input signal using a closed loop control. The input and output signal of the closed loop control are logically combined in accordance with first and second combinatory logic to generate first and second control signals. The first and second control signals selectively activate first and second current sources, respectively. The current supplied by the first current source charges a capacitance controlling the closed loop control, while the current supplied by the second current source discharges the capacitance. By selecting the types of the combinatory logics as well as the ratio of the currents supplied by the first and second current sources, the phase shift of the output signal with respect to the input signal can be variably adapted to individual requirements.

Abstract: For synchronising the data transmission between a CMOS circuit (1) and a bipolar circuit (2) a DLL (delayed lock loop) is provided which sets a phase deviation between the operating clocks (CLK1, CLK2) of the two circuits (1, 2), and changes the phase of at least one of the two clocks (CLK1, CLK2) according to this phase deviation, until said the two clocks are in phase, in such a way that the data (DATA1) provided by the first circuit (1) can then be taken on by the second circuit (2). To this end, the DLL circuit comprises a phase detector (6), a loop filter (7) and an adjustable element (8).

Abstract: The novel frequency divider has an adjustable divider ratio. Such circuits are subject to demands for ever higher clock frequencies. The circuit generates the output signal in a blockwise manner and converts it into a sequential signal in a parallel-serial converter on the output side and outputs it in a bitwise manner. As a result, the essential part of the frequency divider circuit can be operated with a slower frequency than the input frequency, which in turn enables higher input frequencies.

Abstract: The novel frequency divider has an adjustable divider ratio. Such circuits are subject to demands for ever higher clock frequencies. The circuit generates the output signal in a blockwise manner and converts it into a sequential signal in a parallel-serial converter on the output side and outputs it in a bitwise manner. As a result, the essential part of the frequency divider circuit can be operated with a slower frequency than the input frequency, which in turn enables higher input frequencies.

Abstract: A circuit configuration for testing functional units in digital integrated circuits by means of test signals includes at least one OR switching element having inputs and an output. At least one of the inputs of the at least one OR switching element is occupied with signals to be tested. At least one further input of the at least one OR switching element is occupied with selection signals.

Abstract: A circuit configuration for generating combinatorial logic functions includes a plurality of cascading circuit blocks, which are each formed of a 1-out-of-4 multiplexer and an inverter. Control inputs of the multiplexer are acted upon by input variables having a higher significance and data inputs are acted upon by a logical zero, a logical one, least significant input variables or inverted least significant input variables, in dependence on a linking function.

Abstract: A circuit for the generation of combinatorial logic variables, having multiplexers and inverters, which has, for each input state defined by a combination of input variables, a uniquely defined output state defined by at least one output variable including first input variables of lower weighting; blocks of intermediate variables of the same size generated by the input variables of lower weighting, forming with logic combinations having switching behavior determined by further input variables of higher weightings.