Patents by Inventor Josef Maerz
Josef Maerz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11903132Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a laminate inlay embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the laminate inlay and configured to distribute a load current switched by the laminate inlay. A fourth metal layer is positioned between the second metal layer and the laminate inlay and configured as a primary thermal conduction path for heat generated by the laminate inlay during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.Type: GrantFiled: March 17, 2023Date of Patent: February 13, 2024Assignee: Infineon Technologies AGInventors: Petteri Palm, Martin Benisek, Liu Chen, Frank Daeche, Josef Maerz
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Publication number: 20230240012Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a laminate inlay embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the laminate inlay and configured to distribute a load current switched by the laminate inlay. A fourth metal layer is positioned between the second metal layer and the laminate inlay and configured as a primary thermal conduction path for heat generated by the laminate inlay during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.Type: ApplicationFiled: March 17, 2023Publication date: July 27, 2023Inventors: Petteri Palm, Martin Benisek, Liu Chen, Frank Daeche, Josef Maerz
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Patent number: 11632860Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a power device embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the power device and configured to distribute a load current switched by the power device. A fourth metal layer is positioned between the second metal layer and the power device and configured as a primary thermal conduction path for heat generated by the power device during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.Type: GrantFiled: October 25, 2019Date of Patent: April 18, 2023Assignee: Infineon Technologies AGInventors: Petteri Palm, Martin Benisek, Liu Chen, Frank Daeche, Josef Maerz
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Publication number: 20230051100Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.Type: ApplicationFiled: November 3, 2022Publication date: February 16, 2023Inventors: Bun Kian Tay, Mei Yih Goh, Martin Gruber, Josef Hoeglauer, Michael Juerss, Josef Maerz, Thorsten Meyer, Thorsten Scharf, Chee Voon Tan
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Patent number: 11515244Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.Type: GrantFiled: January 21, 2020Date of Patent: November 29, 2022Assignee: Infineon Technologies AGInventors: Bun Kian Tay, Mei Yih Goh, Martin Gruber, Josef Hoeglauer, Michael Juerss, Josef Maerz, Thorsten Meyer, Thorsten Scharf, Chee Voon Tan
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Patent number: 11393743Abstract: A semiconductor device includes a conductive frame comprising a die attach surface that is substantially planar, a semiconductor die comprising a first load on a rear surface and a second terminal disposed on a main surface, a first conductive contact structure disposed on the die attach surface, and a second conductive contact structure on the main surface. The first conductive contact structure vertically extends past a plane of the main surface of the semiconductor die. The first conductive contact structure is electrically isolated from the main surface of the semiconductor die by an electrical isolation structure. An upper surface of the electrical isolation structure is below the main surface of the semiconductor die.Type: GrantFiled: December 18, 2019Date of Patent: July 19, 2022Assignee: Infineon Technologies AGInventors: Stuart Cardwell, Chee Yang Ng, Josef Maerz, Clive O'Dell, Mark Pavier
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Publication number: 20220122906Abstract: A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.Type: ApplicationFiled: September 27, 2021Publication date: April 21, 2022Applicant: Infineon Technologies AGInventors: Sergey YUFEREV, Paul Armand Asentista CALO, Theng Chao LONG, Josef MAERZ, Chee Yang NG, Petteri PALM, Wae Chet YONG
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Patent number: 11302613Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.Type: GrantFiled: July 9, 2020Date of Patent: April 12, 2022Assignee: Infineon Technologies AGInventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan
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Publication number: 20210193560Abstract: A semiconductor device includes a conductive frame comprising a die attach surface that is substantially planar, a semiconductor die comprising a first load on a rear surface and a second terminal disposed on a main surface, a first conductive contact structure disposed on the die attach surface, and a second conductive contact structure on the main surface. The first conductive contact structure vertically extends past a plane of the main surface of the semiconductor die. The first conductive contact structure is electrically isolated from the main surface of the semiconductor die by an electrical isolation structure. An upper surface of the electrical isolation structure is below the main surface of the semiconductor die.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Inventors: Stuart Cardwell, Chee Yang Ng, Josef Maerz, Clive O'Dell, Mark Pavier
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Publication number: 20210166998Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.Type: ApplicationFiled: February 16, 2021Publication date: June 3, 2021Inventors: Thorsten Scharf, Martin Gruber, Josef Hoeglauer, Michael Juerss, Josef Maerz, Thorsten Meyer, Bun Kian Tay
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Publication number: 20210127490Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a power device embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the power device and configured to distribute a load current switched by the power device. A fourth metal layer is positioned between the second metal layer and the power device and configured as a primary thermal conduction path for heat generated by the power device during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.Type: ApplicationFiled: October 25, 2019Publication date: April 29, 2021Inventors: Petteri Palm, Martin Benisek, Liu Chen, Frank Daeche, Josef Maerz
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Patent number: 10964628Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.Type: GrantFiled: February 21, 2019Date of Patent: March 30, 2021Assignee: Infineon Technologies AGInventors: Thorsten Scharf, Martin Gruber, Josef Hoeglauer, Michael Juerss, Josef Maerz, Thorsten Meyer, Bun Kian Tay
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Publication number: 20210020547Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region which forms part of an electrical connection to the second load terminal.Type: ApplicationFiled: July 17, 2019Publication date: January 21, 2021Inventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan
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Publication number: 20210020550Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.Type: ApplicationFiled: July 9, 2020Publication date: January 21, 2021Inventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan
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Patent number: 10886199Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region which forms part of an electrical connection to the second load terminal.Type: GrantFiled: July 17, 2019Date of Patent: January 5, 2021Assignee: Infineon Technologies AGInventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan
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Patent number: 10770399Abstract: A semiconductor package includes a frame having an insulative body with a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body. A thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces. The thermally and/or electrically conductive material provides a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body. A semiconductor die attached to the frame at the first main surface of the insulative body is electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body. A corresponding method of manufacture is also described.Type: GrantFiled: February 13, 2019Date of Patent: September 8, 2020Assignee: Infineon Technologies AGInventors: Chee Yang Ng, Hock Siang Chua, Stefan Macheiner, Josef Maerz, Nurfarena Othman, Joseph Victor Soosai Prakasam, Hong Hock Tay
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Publication number: 20200273790Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.Type: ApplicationFiled: January 21, 2020Publication date: August 27, 2020Inventors: Bun Kian Tay, Mei Yih Goh, Martin Gruber, Josef Hoeglauer, Michael Juerss, Josef Maerz, Thorsten Meyer, Thorsten Scharf, Chee Voon Tan
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Publication number: 20200273781Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.Type: ApplicationFiled: February 21, 2019Publication date: August 27, 2020Inventors: Thorsten Scharf, Martin Gruber, Josef Hoeglauer, Michael Juerss, Josef Maerz, Thorsten Meyer, Bun Kian Tay
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Publication number: 20200258842Abstract: A semiconductor package includes a frame having an insulative body with a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body. A thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces. The thermally and/or electrically conductive material provides a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body. A semiconductor die attached to the frame at the first main surface of the insulative body is electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body. A corresponding method of manufacture is also described.Type: ApplicationFiled: February 13, 2019Publication date: August 13, 2020Inventors: Chee Yang Ng, Hock Siang Chua, Stefan Macheiner, Josef Maerz, Nurfarena Othman, Joseph Victor Soosai Prakasam, Hong Hock Tay
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Patent number: 7498194Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.Type: GrantFiled: April 11, 2007Date of Patent: March 3, 2009Assignee: Infineon Technologies AGInventors: Nikolaus Bott, Oliver Haeberlen, Manfred Kotek, Joost Larik, Josef Maerz, Ralf Otremba