Abstract: A microelectronic device includes a resistive differential alignment monitor (RDAM), including a first variable-width resistor and a second variable-width resistor, which are members of a conductor level. Each of the resistors include a wide portion and a narrow portion. The RDAM further includes a vertical connector to each of the wide portion and the narrow portion of the first variable-width resistor, and to the wide portion and the narrow portion of the second variable-width resistor. The vertical connectors are members of a vertical connector level. Test terminals are coupled to the vertical connectors. The vertical connectors to the first variable-width resistor and the vertical connectors to the second variable-width resistor are separated by equal distances and are oriented anti-parallel to each other. The RDAM may be used to estimate a misalignment distance between the members of the vertical connector level and the members of the conductor level.

Abstract: A microelectronic device includes a resistive differential alignment monitor (RDAM), including a first variable-width resistor and a second variable-width resistor, which are members of a conductor level. Each of the resistors include a wide portion and a narrow portion. The RDAM further includes a vertical connector to each of the wide portion and the narrow portion of the first variable-width resistor, and to the wide portion and the narrow portion of the second variable-width resistor. The vertical connectors are members of a vertical connector level. Test terminals are coupled to the vertical connectors. The vertical connectors to the first variable-width resistor and the vertical connectors to the second variable-width resistor are separated by equal distances and are oriented anti-parallel to each other. The RDAM may be used to estimate a misalignment distance between the members of the vertical connector level and the members of the conductor level.

Abstract: A microelectronic device includes a resistive differential alignment monitor (RDAM), including a first variable-width resistor and a second variable-width resistor, which are members of a conductor level. Each of the resistors include a wide portion and a narrow portion. The RDAM further includes a vertical connector to each of the wide portion and the narrow portion of the first variable-width resistor, and to the wide portion and the narrow portion of the second variable-width resistor. The vertical connectors are members of a vertical connector level. Test terminals are coupled to the vertical connectors. The vertical connectors to the first variable-width resistor and the vertical connectors to the second variable-width resistor are separated by equal distances and are oriented anti-parallel to each other. The RDAM may be used to estimate a misalignment distance between the members of the vertical connector level and the members of the conductor level.

Abstract: An integrated circuit with first and second resistors comprised of resistor bodies, resistor heads, and resistor buffer regions wherein the resistor buffer regions are disposed between the resistor body and the resistor heads. The width of the first and second resistors is different. The length of the first and second resistor buffer regions is different. The total head resistance which is equal to the resistor head resistance plus the resistor buffer region is equal for both the first and second resistors.

Abstract: An integrated circuit with first and second resistors comprised of resistor bodies, resistor heads, and resistor buffer regions wherein the resistor buffer regions are disposed between the resistor body and the resistor heads. The width of the first and second resistors is different. The length of the first and second resistor buffer regions is different. The total head resistance which is equal to the resistor head resistance plus the resistor buffer region is equal for both the first and second resistors.

Abstract: A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14. Drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.

Abstract: A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14. Drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.

Abstract: A method of adjusting process variables in a processing flow is disclosed. Processed samples are tested to determine sample parameters of the tested samples. The sample parameters are analyzed analyzing in relation to the process variables applied in the processing steps to determine the impact of the process variables on the sample parameters The process variables are modified in an attempt to change the sample parameters towards predetermined target values. And, the sequence of processing steps is repeated with the modified process variables.

Abstract: The object of this invention is to present a field effect transistor by which the drain capacitance per unit gate width can be reduced. The gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14, drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in the respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.

Abstract: A method of adjusting process variables in a processing flow is disclosed. Processed samples are tested to determine sample parameters of the tested samples. The sample parameters are analyzed analyzing in relation to the process variables applied in the processing steps to determine the impact of the process variables on the sample parameters The process variables are modified in an attempt to change the sample parameters towards predetermined target values. And, the sequence of processing steps is repeated with the modified process variables.