Abstract: A Defect Leakage Screen Test apparatus and method is introduced to eliminate or reduce steps in the failure analysis process of memory devices, such as DRAM cells, or to eliminate the necessity for the application of a physical failure analysis on the memory device. Special single bit failures due to leakage current, junction current, or threshold leakage current, are characterized by varying the p-well voltage of the memory device during the read operation of the test. The p-well voltage is varied with a test code Initial Program Load (IPL). Additional logic is provided on the memory IC to decode the IPL logic signals. In order to perform the p-well varying test, the memory device is provided with the following: IPL decoding logic; a reference voltage generator; an IPL voltage reference multiplexor; a p-well voltage feed-back circuit; and a differential amplifier circuit.

Abstract: The voltage detection and control circuit includes a voltage detect circuit having an associated switch point greater than a first predetermined voltage, with the voltage detect circuit being responsive to an input voltage greater than the first predetermined voltage for generating an activation signal; and a clamp control circuit, responsive to the activation signal, for clamping an operating voltage to a second predetermined voltage. The second predetermined voltage may be substantially equal to the first predetermined voltage. A spike filter may be included for suppressing spikes in the activation signal. A clamp stage control circuit is provided for suppressing oscillations in the second predetermined voltage. At least one clamp stage, which may include a delay device, provides the operating voltage to a corresponding circuit component as well as reducing current peaks in the corresponding circuit component.