Abstract: Circuit arrangement for synchronizing a subordinate system, in particular a digital subscriber station, by a superordinate system, in particular a digital exchange, in a PCM time-multiplex telecommunication network. The circuit arrangement operates to evaluate only those synchronization bit combinations which lie at the beginning of a message signal block, thereby avoiding initiation of a re-synchronization during transmission of a block.

Abstract: A method and a circuit arrangement for clock synchronization in the transmission of digital information signals. In the four-wire type transmission of blocks of information signals on a two-wire transmission line it is determined, by phase comparison, whether the first bit in each block of signals (1) falls within a time interval derived from the bit clock signal of the local clock generator; (2) falls within an adjacent time interval or (3) falls within none of such time intervals. Depending upon the results of this comparison, the time relationships are left unchanged, the period of the clock generator is shortened or lengthened one or more times, or a one-time, initial phase equality is established.

Abstract: A communication circuit arrangement for receiving digital intelligence signals as, for example, in a digital switching center of a PCM-time-division multiplex communication network wherein signals are transmitted on circuits connected to digital subscriber stations and the signals are in the form of intelligence signal blocks having at least one intelligence signal word and including a synchronizing word ahead of the intelligence signal word. So as to compensate for the fluctuating phase relationship occurring in the received signals, the first bit of the intelligent block is determined using a signal evaluation device and a clock pulse signal having a phase which is selected using a clock pulse selection circuit and wherein a synchronous counter is set to zero. The counter generates release signals for a plurality of registers for the individual portions of the intelligence block and a comparator test for the presence of a proper synchronizing word.

Abstract: A method for the synchronizing of sending and receiving devices in a PCM telecommunication network employs a counter which is reset by each bit representative of a binary 1 in the received message and which produces a signal for enabling the synchronizing device when it reaches its end count. The counter is incremented by clock pulses produced at the receiving station, and the radix of the counter is selected to exceed the number of bits representative of binary "0"s which can appear consecutively within the message, and the time required for the counter to reach its end count is almost as long as the pause between successive message words.