Patents by Inventor Josep Torrellas

Josep Torrellas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240231925
    Abstract: A computer implemented method manages function execution in a container. A dispatcher in the container running in a computer system executes a function initialization in response to a first request for a function. The dispatcher in the container running in the computer system creates group of handlers in response to receiving a group of requests for the function. The dispatcher in the container running in the computer system sends the group of requests to the group of handlers in response to receiving the group of requests. The dispatcher in the container running in the computer system executes the group of requests using the group of handlers.
    Type: Application
    Filed: October 24, 2022
    Publication date: July 11, 2024
    Inventors: Jovan Stojkovic, Hubertus Franke, Tianyin Xu, Josep Torrellas
  • Publication number: 20240134698
    Abstract: A computer implemented method manages function execution in a container. A dispatcher in the container running in a computer system executes a function initialization in response to a first request for a function. The dispatcher in the container running in the computer system creates group of handlers in response to receiving a group of requests for the function. The dispatcher in the container running in the computer system sends the group of requests to the group of handlers in response to receiving the group of requests. The dispatcher in the container running in the computer system executes the group of requests using the group of handlers.
    Type: Application
    Filed: October 23, 2022
    Publication date: April 25, 2024
    Inventors: Jovan Stojkovic, Hubertus Franke, Tianyin Xu, Josep Torrellas
  • Publication number: 20140095896
    Abstract: A processor includes at least one power domain, each power domain including at least one core that switchably receives power supply from a voltage regulator and switchably receives a clock signal from a clock source, a cache, and at least one control registers having stored thereon data indicating power management states of the at least one power domain and the cache.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Nicholas P. Carter, Joshua B. Fryman, Robert C. Knauerhase, Aditya B. Agrawal, Josep Torrellas
  • Patent number: 7711988
    Abstract: Methods and systems for memory monitoring. A triggering access is detected at one or more monitored memory regions. When a triggering access is detected, a function is accessed for determining a monitoring function, and a monitoring function associated with a particular triggered memory location address is automatically determined.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: May 4, 2010
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Yuanyuan Zhou, Josep Torrellas, Pin Zhou
  • Publication number: 20070006047
    Abstract: Methods and systems for memory monitoring. A triggering access is detected at one or more monitored memory regions. When a triggering access is detected, a function is accessed for determining a monitoring function, and a monitoring function associated with a particular triggered memory location address is automatically determined.
    Type: Application
    Filed: June 14, 2006
    Publication date: January 4, 2007
    Inventors: Yuanyuan Zhou, Josep Torrellas, Pin Zhou