Abstract: In one embodiment an electronic device includes a processor and at least one universal serial bus (USB) subsystem comprising logic, at least partially including hardware logic, configured to detect a connection from a remote electronic device to a USB port of the electronic device, determine whether the USB port of the electronic device is to act as an upstream facing port or a downstream facing port, and in response to a determination that the USB port of the electronic device is to be configured as an upstream facing port, to implement a port mapping process to map the USB port to one of a device controller or a debug controller. Other embodiments may be described.

Abstract: An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR) value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.

Abstract: In one embodiment an electronic device includes a processor and at least one universal serial bus (USB) subsystem comprising logic, at least partially including hardware logic, configured to detect a connection from a remote electronic device to a USB port of the electronic device, determine whether the USB port of the electronic device is to act as an upstream facing port or a downstream facing port, and in response to a determination that the USB port of the electronic device is to be configured as an upstream facing port, to implement a port mapping process to map the USB port to one of a device controller or a debug controller. Other embodiments may be described.

Abstract: An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR) value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.

Abstract: A data packet or payload defined by a first format, is generated and is wrapped with headers as defined by a second format, and is processed through a pass through mechanism for transmission based on the second format. The processing includes adding or encapsulating the payload in the transmission data packet. When receiving the transmitted data packet, the headers may be parsed, and the payload processed.

Abstract: Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.

Abstract: Described within is a power management system for a computing platform that provides additional reductions in power consumption from that provided by only periodically putting the CPU or peripheral devices in low power non-operational states. In particular, the embodiment prevents the OS from generating an interrupt due to timer ticks while in a non-C0 state, until such time as a number of timer ticks have been gathered.

Abstract: Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.

Abstract: Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.

Abstract: In one embodiment, an apparatus to synchronize multiple controllers is disclosed. The apparatus comprises a plurality of controllers, and logic coupled to the plurality of controllers to control one or more controllers of the plurality of controllers to perform fetches simultaneously with one or more other controllers of the plurality of controllers. Other embodiments are also described.

Abstract: A method and apparatus are provided for operating a hot plug system. A first device may determine whether the system is to operate in one of a parallel mode or a serial mode. A second device may control a mode of the chipset based on the determination of the first device. The second device may include logic, a first multiplexer, a second multiplexer, a first converter and a second converter all provided on the chipset.

Abstract: Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.

Abstract: Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.

Abstract: Described within is a power management system for a computing platform that provides additional reductions in power consumption from that provided by only periodically putting the CPU or peripheral devices in low power non-operational states. In particular, the embodiment prevents the OS from generating an interrupt due to timer ticks while in a non-C0 state, until such time as a number of timer ticks have been gathered.

Abstract: Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and the I/O controller. A tag is sent from the I/O controller, after the data, via the first bus through the first port. The tag is received by the memory controller. Completion status of the data write is requested from the I/O controller by a processing unit. The request is sent to the I/O controller via a second bus connected between a second port of the memory controller and the I/O controller. The I/O controller waits for a tag acknowledgment from the memory controller before providing notification to the processing unit that the data write has completed. Therefore, the first bus and the second bus are coherent.

Abstract: An apparatus communicates with an advanced switching (AS) fabric. The apparatus includes a transmit engine that generates a request packet for transmission to the AS fabric. The transmit engine associates a first transaction identifier with the request packet. A receive engine receives a reply packet in response to the request packet. The reply packet contains a second transaction identifier. The receive engine compares the first transaction identifier to the second transaction identifier. If the first transaction identifier matches the second transaction identifier, the receive engine decides to store data from the reply packet at an address associated with the first transaction identifier.

Abstract: One embodiment involves having a processor writing disk drive command information for a number of data transactions to cacheable system memory. The processor then performs a single write transaction to a disk drive host controller. The disk drive host controller then causes a DMA transfer to occur which reads the command information located in system memory and stores the command information in a queue. Once the host controller has the command information, it programs the disk drive with information corresponding to a queue entry over a serial interconnect. The disk drive signals an interrupt after it processes the command information. The disk drive host controller does not forward the interrupt to the processor, but services the interrupt itself. The disk drive host controller reads from the disk drive to determine the disk drive status.

Abstract: A method and apparatus are provided for operating a hot plug system. A first device may determine whether the system is to operate in one of a parallel mode or a serial mode. A second device may control a mode of the chipset based on the determination of the first device. The second device may include logic, a first multiplexer, a second multiplexer, a first converter and a second converter all provided on the chipset.

Abstract: The present invention is a method and system to automatic loading program on a medium into memory for execution. In one embodiment, a mode word is configured. The insertion of the medium into a drive is detected based on the mode word. A program on the medium is started when insertion is detected. In another embodiment, a polling circuit in a chipset detects the insertion of the medium into the drive. A status bit is checked in response to an interrupt generated by the polling circuit. A flag in a memory is updated based on the status bit. A poll request by an operating system is responded.

Abstract: In processor-based systems, loss of ports may be avoided while connecting mass storage drives or devices at a host level. In one embodiment, a slave device (e.g., a cache or an accelerator) may be interposed between a host device and a master storage device (e.g., a disk drive) over a serialized link, providing accelerated communications between the host device and the master storage device through the slave device both coupled on select one of one or more ports available at the host device for device connections.