Abstract: A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.

Abstract: A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

Abstract: Systems and methods for implementing counters in a network processor with cost effective memory are disclosed. Embodiments include systems and methods for implementing counters in a network processor using less expensive memory such as DRAM. A network processor receives packets and implements accounting functions including counting packets in each of a plurality of flow queues. Embodiments include a counter controller that may increment counter values more than once during a R-M-W cycle. Each time a counter controller receives a request to update a counter during a R-M-W cycle that has been initiated for the counter, the counter controller increments the counter value received from memory. The incremented value is written to memory during the write cycle of the R-M-W cycle. A write disable unit disables writes that would otherwise occur during R-M-W cycles initiated for the counter during the earlier initiated R-M-W cycle.

Abstract: Disclosed is a process for the preparation of high molecular weight polyesters by reacting one or more dicarboxylic acids directly with 1,4-cyclohexanedimethanol and, optionally, one or more diols. The process uses an overall diol to dicarboxylic acid molar ratio of about 0.97 to about 1.2 and an incremental addition of either the diacid or diol components. The process provides a shorter total reaction time and, thus, lessens the thermal degradation of polyester which may result in high color and reduced molecular weight.

Abstract: Disclosed is a process for the preparation of high molecular weight polyesters by reacting one or more dicarboxylic acids directly with 1,4-cyclohexanedimethanol and, optionally, one or more diols. The process uses an overall diol to dicarboxylic acid molar ratio of about 0.97 to about 1.2 and an incremental addition of either the diacid or diol components. The process provides a shorter total reaction time and, thus, lessens the thermal degradation of polyester which may result in high color and reduced molecular weight.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes a plurality of control blocks, one for each data buffer, each containing control information to link one buffer to another for transmission. Each of the control blocks has a last bit feature which is a single bit and indicates when the data buffer having the last bit is transmitted. This last bit feature is a bit which can be set to either zero or one. The last bit feature is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer.

Abstract: An interface to interconnect Network Processor and Scheduler chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The messages include FlowEnqueue.request, FlowEnqueue.response, PortEnqueue.request and PortStatus.request.

Abstract: A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.

Abstract: An interface to interconnect chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The chips can be configured in different operational modes which dictates what portion of a frame is to be transmitted between selected chips of the system.

Abstract: Electromagnetic propulsion device as a gun or reversible electric motor having a barrel with a cavity extending its length, an armature in said cavity with a permanent magnetic or energized propulsion bus coil, a plurality of wall conductors orthogonal and circumscribing the cavity distributed between the cavity ends with contact means at the cavity on one end and a bus common with all wall conductors on the other and wherein the magnetic fields of the barrel wall conductor coils immediately before and after the magnetic field source in an armature interacts therewith effecting armature motion. Forward and aft armature current shunts direct current from barrel rails to and from the armature coil with associated propulsion bus-aft shunt circuit means, when extant, and to and from said armature propelling wall conductors via said contacts.

Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.

Abstract: Continuous single-step processes for producing higher molecular weight ketones are disclosed that involve a liquid-phase crossed condensation of an aldehyde with a ketone in the presence of a hydrogenation catalyst and a small amount of a catalyst comprising a concentrated hydroxide or alkoxide of an alkali-metal (from Group 1 or Group IA of the Periodic Table of the Elements) or alkali-earth metal (from Group 2, or Group IIA of the Periodic Table of the Elements), wherein the amount of water provided to the reaction mixture, or reaction zone, is relatively low, with respect to the total initial weight of the reaction mixture. The reaction may be carried out in the absence of solubilizing agents or phase transfer agents. The product mixture is largely free of by-products resulting from further condensation reactions of the desired ketone product or intermediates, and free of the self-condensation products of the reactant aldehyde, that are afterward difficult to remove from the reaction mixture.

Abstract: An optimal code generator for generating structured assembly language expressions is disclosed. Because of the equivalence between unit structured assembly language expressions and the code implementing them, it is possible to represent complex structured assembly language expressions as a vector of unit structured assembly language expressions. A set of rules for systematic manipulation is utilized to allow logical operations on the vector representation of structured assembly language expressions to result in optimal code. Using the equivalence between the code and unit structured assembly language expressions allows the vector representation of a structured assembly language expression to be translated directly into code.

Abstract: A method and apparatus are provided for implementing multiple configurable sub-busses of a point-to-point bus. Each of a plurality of bus interconnects include a transmit interface and a receive interface connected to the point-to-point bus. Each transmit interface includes a transmit buffer and a serializer coupled between the buffer and the point-to-point bus. The transmit buffer provides an asynchronous interface between a transmit source and the serializer. The serializer receives data and control signals from the transmit buffer at a first frequency and transmits data and control signals over the point-to-point bus at a higher second frequency. Transmit steering logic is coupled between the transmit source and each transmit buffer of the plurality of bus interconnects. Transmit steering logic directs data and control signals from transmit source to each selected one of the transmit buffers based upon a selected bus configuration.

Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.

Abstract: A state machine for an assembler capable of processing structured assembly language is disclosed. The state machine for an assembler capable of processing structured assembly language IF constructs includes five states, namely, an IF state, an ELSE state, an END—IF state, an ELSE—IF state, and a SETUP—IF state. In response to recognizing a SETUP—IF clause during the IF state or the ELSE—IF state, the process transitions to the SETUP—IF state. In response to recognizing an ELSE—IF clause during the SETUP—IF state, the process transitions to the ELSE—IF state.

Abstract: This disclosure describes the design and construction of high-precision off-axis optical imaging systems. The disclosure also describes the design and construction of high-precision mounting structures for rigidly holding optical elements in an optical imaging system. The disclosure further describes both a mechanism for highly stable mounting and a technique for high precision focusing of a detector in a complex optical setup. The disclosure even further describes both tooling and a technique used for focusing high precision optical imaging systems. The theory and use of at least these concepts are introduced by examining how these concepts aid the construction and use of a non-contact laser scanning system.

Abstract: Data structures, a method, and an associated transmission system for IP fragmentation and IP reassembly on network processors in order to minimize memory allocation requirements. Frame data for IP fragmentation or reassembly on a network processor is read into buffers to which are associated various control structures. The control structures permit IP fragmentation or reassembly to be accomplished without creating multiple copies of the frame or fragments.

Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure. Communications between the chips are provided by a pair of Chip to Chip Macros, one of each operatively positioned on one of the chips, and a Chip to Chip Bus Interface operatively coupling the Chip to Chip Macros.

Abstract: This disclosure describes the design and construction of high-precision off-axis optical imaging systems. The disclosure also describes the design and construction of high-precision mounting structures for rigidly holding optical elements in an optical imaging system. The disclosure further describes both a mechanism for highly stable mounting and a technique for high precision focusing of a detector in a complex optical setup. The disclosure even further describes both tooling and a technique used for focusing high precision optical imaging systems. The theory and use of at least these concepts are introduced by examining how these concepts aid the construction and use of a non-contact laser scanning system.