Abstract: A two-way set associative cache memory system for a parallel-pipelined computer system uses separate queue structures to hold main memory fetch and store requests generated by the central processing unit (CPU). A memory access unit, coupled between the cache memory system and the CPU selects the next request to be processed by the main memory from between the requests at the heads of the fetch and store queues. The request at the head of the fetch queue is preferred over the request at the head of the store queue unless the memory partition to be used by the fetch request is still busy with a previous request while the partition to be used by the store request is idle. Data retrieved from the main memory replaces data in the cache according to an algorithm that prefers empty pages within a set to pages that contain data and prefers pages that do not have pending update requests scheduled to pages that do have pending update requests scheduled.

Abstract: A two-way set associative cache memory system for a parallel-pipelined computer system uses separate queue structures to hold main memory fetch and store requests generated by the central processing unit (CPU). A memory access unit, coupled between the cache memory system and the CPU selects the next request to be processed by the main memory from between the requests at the heads of the fetch and store queues. The request at the head of the fetch queue is preferred over the request at the head of the store queue unless the memory partition to be used by the fetch request is still busy with a previous request while the partition to be used by the store request is idle. Data retrieved from the main memory replaces data in the cache according to an algorithm that prefers empty pages within a set to pages that contain data and prefers pages that do not have pending update requests scheduled to pages that do have pending update requests scheduled.

Abstract: A referencing unit which creates addresses for main memory. Specifically, this reference unit is pipelined in the manner in which it receives the operators to be executed. Concurrency is achieved by allowing any number of read-type operations to be started before operators that are waiting for a store operation to finish even though these latter operators may appear earlier in the code stream. There are two inputs into the reference unit. Each is provided with a queue, one for receiving operators and address couples and another for receiving the output from the top-of-the-stack mechanism residing in the processor. The former is called an address coupled queue and the latter is called a top-of-stack queue. Since the address couple queue operators require no stack inputs, they enter the reference pipeline, two pipeline levels below where the top-of-stack operators enter the pipeline.

Abstract: An address environment storage unit for a stack-oriented data processor for operating in data sets arranged as structured blocks, or nested pushdown stacks. The address environment storage employs a plurality of sets of display registers such that the current set of display registers does not have to be updated each time the processor moves to a different area of data in memory. The programmer only needs to provide a designation of a lexical level in a particular stack and the offset value from the base of the particular activation record in that stack for addition to obtain actual memory address. When the processor executes a procedure enter operator that calls for a new section of memory in which to operate, a display pointer is changed to point to the set of display registers provided for accessing that new area of memory.