Abstract: An apparatus for diffusing wastewater into a clarifier is disclosed. The apparatus has a rotationally symmetric hollow body having a plurality of flow distributors positioned about a perimeter of the rotationally symmetric hollow body and a baffle extending around a bottom end portion of the rotationally symmetric hollow body. The apparatus is dimensioned to fit within an influent well of the clarifier and be connectable to the clarifier on a top end portion of the rotationally symmetric hollow body. A wastewater treatment system including a clarifier and the apparatus is disclosed. A method of retrofitting a circular clarifier by providing the apparatus is also disclosed.

Abstract: A network switch having at least one port data port interface, a first memory, a second memory, and a memory management unit in connection with the at least one data port interface, the first memory, and the second memory. The memory management unit operates to receive data from the at least one data port interface, determine if the data is to be stored in one of the first memory or the second memory, store the data in one of the first memory or the second memory as a linked list, retrieve the data from one of the first memory or the second memory, and forwards the data for egress.

Abstract: The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a plurality of memory locations configured to store data therein and providing a memory address pool having a plurality of available memory addresses arranged therein, wherein each of the plurality of memory addresses corresponds to a specific memory location. The method further includes the steps of providing a memory address pointer, wherein the memory address pointer indicates a next available memory address in the memory address pool, and reading available memory addresses from the memory address pool using a last in first out operation. The method also includes writing released memory addresses into the memory address pool, adjusting a position of the memory address pointer upon a read or a write operation from the memory address pool.

Abstract: A network switch having at least one port data port interface, a first memory, a second memory, and a memory management unit in connection with the at least one data port interface, the first memory, and the second memory. The memory management unit operates to receive data from the at least one data port interface, determine if the data is to be stored in one of the first memory or the second memory, store the data in one of the first memory or the second memory as a linked list, retrieve the data from one of the first memory or the second memory, and forwards the data for egress.

Abstract: A network switch having at least one port data port interface, a first memory, a second memory, and a memory management unit in connection with the at least one data port interface, the first memory, and the second memory. The memory management unit operates to receive data from the at least one data port interface, determine if the data is to be stored in one of the first memory or the second memory, store the data in one of the first memory or the second memory as a linked list, retrieve the data from one of the first memory or the second memory, and forwards the data for egress.

Abstract: A method and apparatus for managing defects in a memory, wherein the method includes the steps of testing a plurality of memory locations to determine an inoperable memory location and moving a memory address corresponding to the inoperable memory location to a first position in a list of available memory addresses. The method further includes the steps of incrementing an address pointer to a second position in the list of available addresses indicating a next available memory address in the list of available addresses, wherein said step of incrementing an address pointer to a second position operates to remove the memory address stored in the first position from the list of available memory addresses.

Abstract: A method and apparatus for controlling data flow in a network switch, wherein the method includes the steps of determining if a quantity of queued data for a port has exceeded a first predetermined threshold, disabling a data flow to the port if the quantity of queued data is determined to have exceeded the first predetermined threshold, and re-enabling the data flow to the port upon satisfying a predetermined spatial requirement and a predetermined temporal requirement. The apparatus includes at least one queue in connection with the at least one data port interface for receiving data transmitted to the at least one data port interface, and a memory management unit in connection with the at least one queue.

Abstract: A method and apparatus for optimizing access to memory, wherein the method includes the steps of receiving a first request for access to a memory, receiving at least two additional requests for access to the memory, and determining a first clock overhead associated with the first request for access to the memory. The method further includes the steps of determining an additional clock overhead associated with each of the at least two additional requests for access to the memory in conjunction with the first request, determining a combination of requests that can be processed together using an optimized overhead, and processing the combination of requests as a single request with the optimal overhead.

Abstract: A method and apparatus for storing data, the method including the steps of generating a glitchless fractional clock pulse in a circuit and transmitting the glitchless fractional clock pulse from the circuit to a data storage element. The data storage element thereafter stores data in the storage element upon receiving the glitchless fractional clock pulse. The apparatus for storing data includes at least one storage element having a data input, a storage enable input, and a data output, and at least one logic circuit having an activating input, an clock input, and a logic output. The at least one logic circuit generates a glitchless fractional clock pulse on the logic output, wherein the logic output is connected to the storage enable input of the storage element and operating to enable the at least one storage element to store data resident on the data input at an optimally stable time.

Abstract: The present invention is related to a method and apparatus for managingmemory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a plurality of memory locations configured to store data therein and providing a memory address pool having a plurality of available memory addresses arranged therein, wherein each of the plurality of memory addresses corresponds to a specific memory location. The method further includes the steps of providing a memory address pointer, wherein the memory address pointer indicates a next available memory address in the memory address pool, and reading available memory addresses from the memory address pool using a last in first out operation. The method also includes writing released memory addresses into the memory address pool, adjusting a position of the memory address pointer upon a read or a write operation from the memory address pool.

Abstract: The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a plurality of memory locations configured to store data therein and providing a memory address pool having a plurality of available memory addresses arranged therein, wherein each of the plurality of memory addresses corresponds to a specific memory location. The method further includes the steps of providing a memory address pointer, wherein the memory address pointer indicates a next available memory address in the memory address pool, and reading available memory addresses from the memory address pool using a last in first out operation. The method also includes writing released memory addresses into the memory address pool, adjusting a position of the memory address pointer upon a read or a write operation from the memory address pool.

Abstract: A method and apparatus for managing defects in a memory, wherein the method includes the steps of testing a plurality of memory locations to determine an inoperable memory location and moving a memory address corresponding to the inoperable memory location to a first position in a list of available memory addresses. The method further includes the steps of incrementing an address pointer to a second position in the list of available addresses indicating a next available memory address in the list of available addresses, wherein said step of incrementing an address pointer to a second position operates to remove the memory address stored in the first position from the list of available memory addresses.

Abstract: A method and apparatus for managing defects in a memory, wherein the method includes the steps of testing a plurality of memory locations to determine an inoperable memory location and moving a memory address corresponding to the inoperable memory location to a first position in a list of available memory addresses. The method further includes the steps of incrementing an address pointer to a second position in the list of available addresses indicating a next available memory address in the list of available addresses, wherein said step of incrementing an address pointer to a second position operates to remove the memory address stored in the first position from the list of available memory addresses.

Abstract: A method and apparatus for optimizing access to memory, wherein the method includes the steps of receiving a first request for access to a memory, receiving at least two additional requests for access to the memory, and determining a first clock overhead associated with the first request for access to the memory. The method further includes the steps of determining an additional clock overhead associated with each of the at least two additional requests for access to the memory in conjunction with the first request, determining a combination of requests that can be processed together using an optimized overhead, and processing the combination of requests as a single request with the optimal overhead.

Abstract: A method and apparatus for optimizing access to memory, wherein the method includes the steps of receiving a first request for access to a memory, receiving at least two additional requests for access to the memory, and determining a first clock overhead associated with the first request for access to the memory. The method further includes the steps of determining an additional clock overhead associated with each of the at least two additional requests for access to the memory in conjunction with the first request, determining a combination of requests that can be processed together using an optimized overhead, and processing the combination of requests as a single request with the optimal overhead.

Abstract: Methods for separation of substances are provided. The methods include contacting a mixture of at least two components in flowable conditions with mesoporous, crystalline materials termed M41S which also include MCM-41 materials. The mesoporous crystalline materials may be used in separations as is or functionalized.

Abstract: A process is provided for converting feedstock hydrocarbon compounds over a catalyst composition which comprises clay and a zeolite component, at least one of which has been treated with a phosphorus-containing compound, for example, ammonium dihydrogen phosphate or phosphoric acid, and which is spray dried at a low pH, preferably lower than about 3. An embodiment of the present invention comprises an improved catalytic cracking process to produce high octane gasoline and increased lower olefins, especially propylene and butylene.

Abstract: A process is provided for converting feedstock hydrocarbon compounds over a catalyst composition which comprises a molecular sieve material and a boron phosphate-containing matrix. An embodiment of the present invention comprises a catalytic cracking process to produce higher octane gasoline.

Abstract: A layered catalyst contains a core of at least one, and preferably three, molecular sieve components within a shell layer of reduced molecular sieve content. A preferred catalyst consists of a core of a large pore molecular sieve, preferably a dealuminized Y-type zeolite, a shape selective paraffin cracking/isomerization component, preferably HZSM-5, and a shape selective aliphatic aromatization component, preferably gallium ZSM-5, within a shell of an alumina-rich, matrix. The shell can capture metals from the feeds being processed, it can act as a metals sink, and can remove metals form the unit by attrition. The catalyst is preferably prepared by forming the core and then coating or encapsulating the core with a shell having a reduced molecular sieve content. The shell may contain a pillared clay or other very large pore cracking component. The shell may be an attritable coating of an amorphous rare earth oxide, aluminum oxide and aluminum phosphate composite, which traps metals.

Abstract: A process for demetallizing metals contaminated FCC catalyst in an FCC regenerator. A metals getter additive, with higher settling velocity, is added to the regenerator, to remove metals from FCC catalyst by solid-solid interaction. The FCC catalyst forms a light, discrete, dense phase fluidized bed on top of a fluidized bed of additive. FCC catalyst is recycled to the cracking reactor from the top fluidized bed, while additive can be withdrawn from the lower fluidized bed for disposal or for metals recovery and recycle. Additive can be optimized for metals removal and will not dilute the cracking catalyst in the FCC reactor.