Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.

Abstract: An integrated circuit includes logic regions and dynamically adjustable voltage controllers. A voltage controller connected to each logic region enables voltage adjustment while the chip is operating. Each voltage controller has a selector device connected to voltage input lines providing different voltages. A voltage sensor connected to the output of the selector device provides a supply voltage to one of the logic regions. A control circuit dynamically monitors the supply voltage, captures and stores a digital representation of the supply voltage during each cycle of a clock, and tracks variations over time, based on operation of the logic regions. When variations in the supply voltage exceed an operational threshold of one of the logic regions, the control circuit submits a request to a central controller. When the central controller grants permission, the control circuit dynamically adjusts the voltage by enabling the selector device to choose a different voltage input line.

Abstract: A process of optimizing a resistor-2 resistor (R-2R) digital-to-analog converter (DAC) by partial resistor network reconfiguration is disclosed. The method includes analyzing a circuit to determine whether any specifications are outside predetermined limits. The method further includes determining one or more addresses that cause the circuit to be outside of the predetermined limits. The method further includes defining logic to detect address information and control function to alter the circuit to improve the specifications. The method further includes installing the control function into the circuit to improve the specifications.

Abstract: An integrated circuit includes logic regions and dynamically adjustable voltage controllers. A voltage controller connected to each logic region enables voltage adjustment while the chip is operating. Each voltage controller has a selector device connected to voltage input lines providing different voltages. A voltage sensor connected to the output of the selector device provides a supply voltage to one of the logic regions. A control circuit dynamically monitors the supply voltage, captures and stores a digital representation of the supply voltage during each cycle of a clock, and tracks variations over time, based on operation of the logic regions. When variations in the supply voltage exceed an operational threshold of one of the logic regions, the control circuit submits a request to a central controller. When the central controller grants permission, the control circuit dynamically adjusts the voltage by enabling the selector device to choose a different voltage input line.

Abstract: A process of optimizing a resistor-2 resistor (R-2R) digital-to-analog converter (DAC) by partial resistor network reconfiguration is disclosed. The method includes analyzing a circuit to determine whether any specifications are outside predetermined limits. The method further includes determining one or more addresses that cause the circuit to be outside of the predetermined limits. The method further includes defining logic to detect address information and control function to alter the circuit to improve the specifications. The method further includes installing the control function into the circuit to improve the specifications.

Abstract: Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.

Abstract: A resistor-2 resistor (R-2R) digital-to-analog converter with partial resistor network reconfiguration. A circuit includes a plurality of resistor stacks. The circuit also includes a plurality of separation resistors which separate each of the plurality of resistor stacks. The circuit further includes a first selection circuit connected to a first resistor stack of the plurality of resistor stacks and a plurality of selection circuits connected between the plurality of separation resistors. The circuit also includes a termination resistor stack connected to a drain of the first resistor stack.

Abstract: A resistor-2 resistor (R-2R) digital-to-analog converter with resistor network reversal and methods of use are disclosed. A circuit includes a plurality of resistor stacks and a plurality of separation resistors which separate the resistor stacks. The circuit further includes a plurality of selection devices connected to a respective one of the plurality of resistor stacks. The circuit also includes a first termination resistor stack connected to a drain of a first resistor stack of the plurality of resistor stacks and a second termination resistor stack connected to a drain of a last resistor stack of the plurality of resistor stacks. The circuit further includes a first switch connected to the drain of the first resistor stack of the plurality of resistor stacks and an output. The circuit also includes a second switch connected to the drain of the last resistor stack of the plurality of resistor stacks and the output.

Abstract: Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation.

Abstract: A resistor-2 resistor (R-2R) digital-to-analog converter with resistor network reversal and methods of use are disclosed. A circuit includes a plurality of resistor stacks and a plurality of separation resistors which separate the resistor stacks. The circuit further includes a plurality of selection devices connected to a respective one of the plurality of resistor stacks. The circuit also includes a first termination resistor stack connected to a drain of a first resistor stack of the plurality of resistor stacks and a second termination resistor stack connected to a drain of a last resistor stack of the plurality of resistor stacks. The circuit further includes a first switch connected to the drain of the first resistor stack of the plurality of resistor stacks and an output. The circuit also includes a second switch connected to the drain of the last resistor stack of the plurality of resistor stacks and the output.

Abstract: A resistor-2 resistor (R-2R) digital-to-analog converter with partial resistor network reconfiguration. A circuit includes a plurality of resistor stacks. The circuit also includes a plurality of separation resistors which separate each of the plurality of resistor stacks. The circuit further includes a first selection circuit connected to a first resistor stack of the plurality of resistor stacks and a plurality of selection circuits connected between the plurality of separation resistors. The circuit also includes a termination resistor stack connected to a drain of the first resistor stack.

Abstract: Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation.