Patents by Inventor Joseph A. Levert
Joseph A. Levert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6869347Abstract: Fabrication techniques for polishing fibers engaged in grooves on substrates. A protection template assembly is disclosed to protect the unpolished portions of fibers. Chemical mechanical polishing may be used to achieve high fabrication throughput and high polishing uniformity. Optical monitoring may be used to monitor the polishing in real time.Type: GrantFiled: March 5, 2004Date of Patent: March 22, 2005Assignee: Oluma, Inc.Inventors: Vilas Koinkar, Timothy C. Collins, Joannes M. Costa, Joseph A. Levert
-
Publication number: 20040192052Abstract: The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The present invention describes planarization methods for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer tending to dwell in regions of lower surface topography, protecting said lower regions from etching by a combination of chemical and mechanical effects. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions among other additives, thereby hindering the dissolution of interconnect copper into the protective overlayer.Type: ApplicationFiled: November 17, 2003Publication date: September 30, 2004Inventors: Shyama Mukherjee, Joseph Levert, Donald Debear
-
Publication number: 20040171329Abstract: Fabrication techniques for polishing fibers engaged in grooves on substrates. A protection template assembly is disclosed to protect the unpolished portions of fibers. Chemical mechanical polishing may be used to achieve high fabrication throughput and high polishing uniformity. Optical monitoring may be used to monitor the polishing in real time.Type: ApplicationFiled: March 5, 2004Publication date: September 2, 2004Applicant: Oluma, Inc.Inventors: Vilas Koinkar, Timothy C. Collins, Joannes M. Costa, Joseph A. Levert
-
Patent number: 6771874Abstract: A method of placing a fiber on a substrate includes holding at least one fiber under tension, aligning the held fiber with a groove formed into a substrate, moving the substrate towards the fiber to place the fiber in the groove, fixing the position of the fiber under tension in the groove, and releasing the fiber.Type: GrantFiled: May 17, 2002Date of Patent: August 3, 2004Assignee: Otuma, Inc.Inventors: Joseph A. Levert, Michael Talmadge
-
Publication number: 20040124438Abstract: An electronic component contemplated comprises a) a substrate layer, b) a dielectric layer coupled to the substrate layer, c) a barrier layer coupled to the dielectric layer, d) a conductive layer coupled to the barrier layer, and e) a protective layer coupled to the conductive layer. The electronic component contemplated herein can be produced by a) providing a substrate; b) coupling a dielectric layer to the substrate; c) coupling a barrier layer to the dielectric layer; d) coupling a conductive layer to the barrier layer; and e) coupling a protective layer to the conductive layer. The protective layer may then be cured to a desirable hardness.Type: ApplicationFiled: May 22, 2003Publication date: July 1, 2004Inventors: Shyama Mukherjee, Joseph Levert, Donald BeBear
-
Patent number: 6719608Abstract: Fabrication techniques for polishing fibers engaged in grooves on substrates. A protection template assembly is disclosed to protect the unpolished portions of fibers. Chemical mechanical polishing may be used to achieve high fabrication throughput and high polishing uniformity. Optical monitoring may be used to monitor the polishing in real time.Type: GrantFiled: April 19, 2002Date of Patent: April 13, 2004Assignee: Oluma, Inc.Inventors: Vilas Koinkar, Timothy C. Collins, Joannes M. Costa, Joseph A. Levert
-
Publication number: 20040046148Abstract: Chemical mechanical planarization or spin etch planarization of surfaces of copper, tantalum and tantalum nitride is accomplished by means of the chemical formulations of the present invention. The chemical formulations may optionally include abrasive particles and which may be chemically reactive or inert. Contact or non-contact CMP may be performed with the present chemical formulations. Substantially 1:1 removal rate selectivity for Cu and Ta/TaN is achieved.Type: ApplicationFiled: May 27, 2003Publication date: March 11, 2004Inventors: Fan Zhang, Dan Towery, Joseph Levert, Shyama Mukherjee, Yanpei Deng
-
Patent number: 6696358Abstract: The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The present invention describes planarization methods for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer tending to dwell in regions of lower surface topography, protecting said lower regions from etching by a combination of chemical and mechanical effects. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions among other additives, thereby hindering the dissolution of interconnect copper into the protective overlayer.Type: GrantFiled: January 23, 2001Date of Patent: February 24, 2004Assignee: Honeywell International Inc.Inventors: Shyama Mukherjee, Joseph Levert, Donald Debear
-
Patent number: 6630433Abstract: Chemical mechanical planarization or spin etch planarization of surfaces of copper, tantalum and tantalum nitride is accomplished by means of the chemical formulations of the present invention. The chemical formulations may optionally include abrasive particles and which may be chemically reactive or inert. Contact or non-contact CMP may be performed with the present chemical formulations. Substantially 1:1 removal rate selectivity for Cu and Ta/TaN is achieved.Type: GrantFiled: December 20, 2000Date of Patent: October 7, 2003Assignee: Honeywell International Inc.Inventors: Fan Zhang, Daniel L. Towery, Joseph A. Levert, Shyama P. Mukherjee
-
Patent number: 6600229Abstract: An electronic component contemplated comprises a) a substrate layer, b) a dielectric layer coupled to the substrate layer, c) a barrier layer coupled to the dielectric layer, d) a conductive layer coupled to the barrier layer, and e) a protective layer coupled to the conductive layer. The electronic component contemplated herein can be produced by a) providing a substrate; b) coupling a dielectric layer to the substrate; c) coupling a barrier layer to the dielectric layer; d) coupling a conductive layer to the barrier layer; and e) coupling a protective layer to the conductive layer. The protective layer may then be cured to a desirable hardness.Type: GrantFiled: May 1, 2001Date of Patent: July 29, 2003Assignee: Honeywell International Inc.Inventors: Shyama Mukherjee, Joseph Levert, Donald DeBear
-
Publication number: 20030133691Abstract: A method of placing a fiber on a substrate includes holding at least one fiber under tension, aligning the held fiber with a groove formed into a substrate, moving the substrate towards the fiber to place the fiber in the groove, fixing the position of the fiber under tension in the groove, and releasing the fiber.Type: ApplicationFiled: May 17, 2002Publication date: July 17, 2003Inventors: Joseph A. Levert, Michael Talmadge
-
Publication number: 20030073311Abstract: The present invention describes methods and chemical compositions for the spin etch planarization of surfaces, particularly copper and tantalum. An etching solution is brought into contact with the upper face of a spinning wafer through a nozzle, preferably an oscillating nozzle. The etching solution has a composition that oxidizes the spinning surface, forming a passivation layer thereon. The etching solution further contains reactants for removing the passivation layer exposing the underlying surface to further reaction, leading to the desired etching of the surface. The characteristics of the etching solution are adjusted such that reactant diffusion to lower regions of the surface limits the rate of etching. Faster reaction occurs at higher regions of the surface lying in more rapidly moving etching solution resulting in the desired planarization.Type: ApplicationFiled: August 15, 2002Publication date: April 17, 2003Inventors: Joseph Levert, Daniel Towery
-
Publication number: 20030054616Abstract: An electronic device comprises a substrate with a trench having a lower portion and a top portion. The lower portion of the trench is filled with a cured spin-on compound, while the top portion is filled with a chemical vapor-deposited compound. Preferably, the chemical vapor-deposited compound has a surface that is substantially coplanar with the surface of the substrate. Particularly preferred methods of fabricating such devices include a step in which a trench is formed in the substrate, and in which a first compound is deposited in the trench by spin-on deposition. The first compound is partially removed from the trench to a level below the surface of the substrate, and in a further step, a second compound is deposited onto the upper surface of the first compound by chemical vapor deposition.Type: ApplicationFiled: August 29, 2001Publication date: March 20, 2003Applicant: Honeywell International Inc.Inventors: Denis H. Endisch, Joseph Levert
-
Publication number: 20020117758Abstract: An electronic component contemplated comprises a) a substrate layer, b) a dielectric layer coupled to the substrate layer, c) a barrier layer coupled to the dielectric layer, d) a conductive layer coupled to the barrier layer, and e) a protective layer coupled to the conductive layer. The electronic component contemplated herein can be produced by a) providing a substrate; b) coupling a dielectric layer to the substrate; c) coupling a barrier layer to the dielectric layer; d) coupling a conductive layer to the barrier layer; and e) coupling a protective layer to the conductive layer. The protective layer may then be cured to a desirable hardness.Type: ApplicationFiled: May 1, 2001Publication date: August 29, 2002Inventors: Shyama Mukherjee, Joseph Levert, Donald Debear
-
Publication number: 20020096770Abstract: The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The present invention describes planarization methods for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer tending to dwell in regions of lower surface topography, protecting said lower regions from etching by a combination of chemical and mechanical effects. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions among other additives, thereby hindering the dissolution of interconnect copper into the protective overlayer.Type: ApplicationFiled: January 23, 2001Publication date: July 25, 2002Inventors: Shyama Mukherjee, Joseph Levert, Donald Debear
-
Patent number: 6407006Abstract: An apparatus for planarizing or patterning a dielectric film on a substrate is provided. The apparatus includes a press for applying contact pressure to an operably connected compression tool. The compression tool has a working face that is planar or patterned. A controller for regulating the position, timing and force applied by the compression tool to the dielectric film is also provided. There is also provided a support, with an optional workpiece holder for supporting the substrate and dielectric film during contact with the compression tool. Methods of using the apparatus, as well as planarized and/or patterned dielectric films are also provided.Type: GrantFiled: April 14, 2000Date of Patent: June 18, 2002Assignee: Honeywell International, Inc.Inventors: Joseph A Levert, Daniel Lynne Towery, Denis Endisch
-
Publication number: 20020020833Abstract: Chemical mechanical planarization or spin etch planarization of surfaces of copper, tantalum and tantalum nitride is accomplished by means of the chemical formulations of the present invention. The chemical formulations may optionally include abrasive particles and which may be chemically reactive or inert. Contact or non-contact CMP may be performed with the present chemical formulations. Substantially 1:1 removal rate selectivity for Cu and Ta/TaN is achieved.Type: ApplicationFiled: December 20, 2000Publication date: February 21, 2002Inventors: Fan Zhang, Daniel L. Towery, Joseph A. Levert, Shyama P. Mukherjee
-
Publication number: 20010054706Abstract: The present invention describes methods and chemical compositions for the spin etch planarization of surfaces, particularly copper and tantalum. An etching solution is brought into contact with the upper face of a spinning wafer through a nozzle, preferably an oscillating nozzle. The etching solution has a composition that oxidizes the spinning surface, forming a passivation layer thereon. The etching solution further contains reactants for removing the passivation layer exposing the underlying surface to further reaction, leading to the desired etching of the surface. The characteristics of the etching solution are adjusted such that reactant diffusion to lower regions of the surface limits the rate of etching. Faster reaction occurs at higher regions of the surface lying in more rapidly moving etching solution resulting in the desired planarization.Type: ApplicationFiled: July 19, 1999Publication date: December 27, 2001Inventors: JOSEPH A. LEVERT, DANIEL L. TOWERY
-
Publication number: 20010036749Abstract: An apparatus for planarizing or patterning a dielectric film on a substrate is provided. The apparatus includes a press for applying contact pressure to an operably connected compression tool. The compression tool has a working face that is planar or patterned. A controller for regulating the position, timing and force applied by the compression tool to the dielectric film is also provided. There is also provided a support, with an optional workpiece holder for supporting the substrate and dielectric film during contact with the compression tool. Methods of using the apparatus, as well as planarized and/or patterned dielectric films are also provided.Type: ApplicationFiled: May 18, 2001Publication date: November 1, 2001Inventors: Joseph A. Levert, Daniel Lynne Towery, Denis Endisch