Abstract: An audio system includes a processor including an input configured to: receive a baseband audio signal and modulate the baseband audio signal to create a modulated audio signal comprising audio signal frequency components in a first frequency range; clip the modulated audio signal to create a clipped, modulated audio signal the clipped modulated audio signal comprising the audio signal frequency components in the first range and further comprising distortion frequency components outside the first frequency range. The system can further be configured to filter the clipped, modulated audio signal to remove frequency components outside the first frequency to remove distortion components outside that frequency range.

Abstract: An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine.

Abstract: An audio system includes a processor including an input configured to: receive a baseband audio signal and modulate the baseband audio signal to create a modulated audio signal comprising audio signal frequency components in a first frequency range; clip the modulated audio signal to create a clipped, modulated audio signal the clipped modulated audio signal comprising the audio signal frequency components in the first range and further comprising distortion frequency components outside the first frequency range. The system can further be configured to filter the clipped, modulated audio signal to remove frequency components outside the first frequency to remove distortion components outside that frequency range.

Abstract: Described embodiments process data packets received that include a source address and at least one destination address. If the destination address is stored in a memory of an I/O adapter, the received data packet is processed in accordance with bridging rules associated with each destination address stored in the I/O adapter memory. If the destination address is not stored in the I/O adapter memory, the I/O adapter sends a task message to a processor to determine whether the destination address is stored in an address table stored in a shared memory of the network processor. The I/O adapter memory has lower access latency than the address table. If the destination address is stored in the address table, the received data packet is processed in accordance with bridging rules stored in the address table and the bridging rules stored in the I/O adapter memory are updated.

Abstract: Described embodiments provide a method of operating a network processor coupled to a network via a communication link. An input/output adapter receives a data packet. A classification module provides control values of the data packet to a statistics module. The statistics module determines (i) updatable statistics based on the control values, and (ii) an address of a statistics bin in a memory of the network processor corresponding to the statistics. Updated values of the statistics are stored at the corresponding address. Values at selected addresses are processed by a control processor of the network processor, generating traffic characteristics for the data packets. The control processor adjusts operation of the network processor based on the traffic characteristics.

Abstract: An apparatus having a parser and a circuit is disclosed. The parser is configured to generate a source address, a destination address and information by parsing a packet received via one of a plurality of networks. The circuit is configured to search a plurality of memories in parallel during a single cycle of operation in the apparatus. The searching includes a plurality of lookups in the memories of a plurality of data sets associated with the source address, the destination address and the information, respectively. The circuit is also configured to bridge the packet between the networks in response to the data sets.

Abstract: An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine.

Abstract: An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine.

Abstract: Described embodiments provide a system having at least two network processors that each have a plurality of processing modules. The processing modules process a packet in a task pipeline by transmitting task messages to other processing modules on a task ring, the task messages related to desired processing of the packet. A series of tasks within a network processor may result in no processing or reduced processing for certain processing modules creating a virtual pipeline depending on the packet received by the network processor. At least two of the network processors communicate tasks. This communication allows ter the extension of the virtual pipeline of or IC network processor to at least two network processors.

Abstract: A switch includes registers, a parser and port selection logic. The registers store an address in multiple locations. The address defines a bridge domain. Each bridge domain defines a set of switch ports. The parser identifies when a received frame includes a virtual local area network (VLAN) identifier. The parser uses the VLAN identifier to locate the address in the registers. The port selection logic is responsive to one of a first index from a first table that includes port identifiers and the bridge domain and a second index from a second table that includes VLAN identifiers. The switch is configured by defining an address scheme, inserting an address field in the first and second tables, and generating maps from the tables. The maps direct the port selection logic to direct received frames to desired port(s).

Abstract: In one embodiment, a four-input, four-output bin adder is disclosed. The bin adder comprises a two-by-three, multi-stage, cascaded array of two-input, two-output adder circuits. Each of the bin-adder input signals comprises a numeric data value and an associated address, and the bin adder is adapted to add together (a.k.a. accumulate) the numeric values of only those inputs signals having addresses that are the same. In particular, the inputs and outputs of the two-input, two-output adder circuits are connected together in such a way that each input signal is compared to every other input signal, in a round-robin configuration. If the associated addresses match, then the input signals' numeric data values are added (i.e., accumulated) and output as a single signal comprising the sum of the numeric data values and the common address.

Abstract: An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine.

Abstract: An apparatus having a parser and a circuit is disclosed. The parser is configured to generate a source address, a destination address and information by parsing a packet received via one of a plurality of networks. The circuit is configured to search a plurality of memories in parallel during a single cycle of operation in the apparatus. The searching includes a plurality of lookups in the memories of a plurality of data sets associated with the source address, the destination address and the information, respectively. The circuit is also configured to bridge the packet between the networks in response to the data sets.

Abstract: An apparatus for supporting multicast address learning in a network processor includes a task parameter decoder receiving the packet and determining parameters of the packet, a plurality of unlearned address counters recording a number of the packets to be multicast, a correlator determining destination addresses of the packet, a multicast replicator replicating the packet multiple times, and a task generator generating a generated packet with a bitmap and sending out the generated packet to an I/O adaptor over a task ring interface of the network processor. If the packet is unlearned, the unlearned address counter is then incremented and the unlearned packet is sent back to a special queue in the I/O adaptor over the task ring interface with an index to the bitmap for replicating by the multicast replicator, after replicating, the unlearned address counter is decremented. Methods for replicating unlearned/learned multicast packets within a network processor are included.

Abstract: In described embodiments, a timestamp generator includes a fixed clock domain driven by a fixed frequency clock, a core clock domain, coupled to the fixed clock domain, which is driven by a core clock whose frequency is adjustable during an operation of the timestamp generator. A timestamp logic operating in the core clock domain generates a timestamping output of the timestamp generator. A rate generator operating in both the fixed clock domain and the core clock domain generates per clock cycle increments in the fixed clock domain and transfers carry units from the fixed clock domain into the core clock domain, and a timestamp increment generation of the timestamp logic is clocked by the fixed frequency clock provided by the rate generator. A method for enabling timestamp in an ASIC to be accurate with system clock changes is also described.

Abstract: A scalable packet switch possessing a multiport memory, a multiport memory manager, two or more input/output (I/O) ports, and two or more switch engines. Each switch engine is associated with one or more I/O ports, and is adapted to receive inbound packets and transmit outbound packets via the associated I/O ports. Inbound packets are stored in a shared packet buffer. Each switch engine is further adapted to (i) determine (i.e., bridge) the outbound I/O port(s) for received inbound packets by consulting a shared bridging table and (ii) schedule outbound packets for transmission, independently and in parallel with other switch engines. The shared packet buffer and shared bridging table are stored in the multiport memory and shared by all switch engines. The multiport memory manager allocates/de-allocates memory blocks within the multiport memory.

Abstract: Described embodiments provide a system having at least two network processors that each have a plurality of processing modules. The processing modules process a packet in a task pipeline by transmitting task messages to other processing modules on a task ring, the task messages related to desired processing of the packet. A series of tasks within a network processor may result in no processing or reduced processing for certain processing modules creating a virtual pipeline depending on the packet received by the network processor. At least two of the network processors communicate tasks. This communication allows ter the extension of the virtual pipeline of or IC network processor to at least two network processors.

Abstract: An apparatus for supporting multicast address learning in a network processor includes a task parameter decoder receiving the packet and determining parameters of the packet, a plurality of unlearned address counters recording a number of the packets to be multicast, a correlator determining destination addresses of the packet, a multicast replicator replicating the packet multiple times, and a task generator generating a generated packet with a bitmap and sending out the generated packet to an I/O adaptor over a task ring interface of the network processor. If the packet is unlearned, the unlearned address counter is then incremented and the unlearned packet is sent back to a special queue in the I/O adaptor over the task ring interface with an index to the bitmap for replicating by the multicast replicator, after replicating, the unlearned address counter is decremented. Methods for replicating unlearned/learned multicast packets within a network processor are included.

Abstract: Described embodiments provide a method of operating a network processor coupled to a network via a communication link. An input/output adapter receives a data packet. A classification module provides control values of the data packet to a statistics module. The statistics module determines (i) updatable statistics based on the control values, and (ii) an address of a statistics bin in a memory of the network processor corresponding to the statistics. Updated values of the statistics are stored at the corresponding address. Values at selected addresses are processed by a control processor of the network processor, generating traffic characteristics for the data packets. The control processor adjusts operation of the network processor based on the traffic characteristics.

Abstract: A scalable packet switch possessing a multiport memory, a multiport memory manager, two or more input/output (I/O) ports, and two or more switch engines. Each switch engine is associated with one or more I/O ports, and is adapted to receive inbound packets and transmit outbound packets via the associated I/O ports. Inbound packets are stored in a shared packet buffer. Each switch engine is further adapted to (i) determine (i.e., bridge) the outbound I/O port(s) for received inbound packets by consulting a shared bridging table and (ii) schedule outbound packets for transmission, independently and in parallel with other switch engines. The shared packet buffer and shared bridging table are stored in the multiport memory and shared by all switch engines. The multiport memory manager allocates/de-allocates memory blocks within the multiport memory.