Abstract: An address translation unit includes a translation lookaside buffer (TLB), a miss queue, and a control unit. The TLB may store a plurality of address translations. The miss queue may store received address translation requests that missed in the TLB. The miss queue includes a plurality of entries. At least some entries may each store a respective address translation request and a corresponding identifier. The corresponding identifier of a given entry identifies another entry in the miss queue that stores another respective address translation request having a process ordering constraint that is the same as a process ordering constraint of the respective address translation request in the given entry. Address translations having a same ordering constraint that are linked together via the identifier belong to the same virtual miss queue. The control unit may process the received address translation requests in an order dependent upon the identifier.

Abstract: In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the request sources that use the TLB. For requests from the subset, the reserved section may be used and a location in the reserved section may be allocated to store a translation for a request from the subset that misses in the TLB. For requests for other request sources, the non-reserved section or sections may be used. In one embodiment, each way of the reserved section may be assigned to a different one of the request sources in the subset.

Abstract: In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the request sources that use the TLB. For requests from the subset, the reserved section may be used and a location in the reserved section may be allocated to store a translation for a request from the subset that misses in the TLB. For requests for other request sources, the non-reserved section or sections may be used. In one embodiment, each way of the reserved section may be assigned to a different one of the request sources in the subset.

Abstract: In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the request sources that use the TLB. For requests from the subset, the reserved section may be used and a location in the reserved section may be allocated to store a translation for a request from the subset that misses in the TLB. For requests for other request sources, the non-reserved section or sections may be used. In one embodiment, each way of the reserved section may be assigned to a different one of the request sources in the subset.

Abstract: An address translation unit includes a translation lookaside buffer (TLB), a miss queue, and a control unit. The TLB may store a plurality of address translations. The miss queue may store received address translation requests that missed in the TLB. The miss queue includes a plurality of entries. At least some entries may each store a respective address translation request and a corresponding identifier. The corresponding identifier of a given entry identifies another entry in the miss queue that stores another respective address translation request having a process ordering constraint that is the same as a process ordering constraint of the respective address translation request in the given entry. Address translations having a same ordering constraint that are linked together via the identifier belong to the same virtual miss queue. The control unit may process the received address translation requests in an order dependent upon the identifier.

Abstract: In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the request sources that use the TLB. For requests from the subset, the reserved section may be used and a location in the reserved section may be allocated to store a translation for a request from the subset that misses in the TLB. For requests for other request sources, the non-reserved section or sections may be used. In one embodiment, each way of the reserved section may be assigned to a different one of the request sources in the subset.

Abstract: Methods and apparatus for using a store allocate policy to eliminate the stale data problem in a direct mapped, write-through virtual data cache. A hardware mechanism provided by the present invention, ensures that a single cache location associated with more than one virtual address does not become stale with respect to the main memory. By using a store allocate policy along with a write-through virtual cache, each time a store miss occurs, the data cache location for which the store miss occurred will be updated with new data brought back from the main memory along with a new cache tag. The store allocate policy for a write-through virtual data cache is implemented by a data cache controller. Thus, using this cache policy, the cache is updated along with the main memory even after a store miss.

Abstract: A cache memory is arranged using write buffering circuitry. This cache memory arrangement comprises a Random Access Memory (RAM) array for memory storage operated under the control of a control circuit which receives input signals representing address information, write control signals, and write cancel signals. At least one address register buffer is coupled to the address input of the RAM, while at least one data register buffer is coupled to the data input of the RAM. Thus, in accordance with the present invention, addresses to be accessed in the RAM, as well as data to be written to the RAM, are buffered prior to being coupled to the RAM. As a result, systems utilizing the cache memory arrangement of the present invention need not stall or delay the output of information toward the RAM in order to check for a cache hit or miss. Such determinations can advantageously be made while the relevant address and data are in the register buffers en route to the RAM.

Abstract: Bypassing of data from a main storage unit to an instruction and operand processing unit around an intermediate storage unit improves performance in a data processing system. The instruction and operand processing unit supplies requests for operands to the intermediate storage unit or cache. If the line is missing from the cache, the request operand is retrieved from the main storage unit. A bypass data path is connected between the main storage unit, prior to error detecting means in the cache, and the instruction and operand processing unit for transferring requested operands to the instruction and operand processing unit directly. Control, coupled to receive requests for operands and to the instruction and operand processing unit, signals the instruction and operand processing unit to receive the requested operands from the bypass data path when the data includes a requested operand.

Abstract: The reporting of errors that are detected when data which contains an error is moved from a high speed buffer memory array to a main storage array is deferred so that the error checking and correcting logic associated with the main storage memory array will recognize the data as containing an error generated in the buffer array and report the error only when the data is moved out of the main store. In this manner, a process relevant to the erroneous data is assured to be in operation when the error is reported.

Abstract: The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first circuitry for storing multiple digital first signals; second circuitry for storing the multiple digital first signals and adapted for storing at least one digital second signal; third circuitry for transmitting the multiple digital first signals substantially from the first circuitry to the second circuitry; fourth circuitry for providing the at least one digital second signal, in the course of the transmitting of the first signals by the third circuitry, in response to an occurrence of one or more errors in one or more of the multiple digital first signals; fifth circuitry for transmitting the multiple digital first signals substantially from the second circuitry to the first means; and sixth circuitry adapted for receiving the at least one digital second signal in the course of the transmitting of the multiple digital first signals by the fifth circuitry and for provid

Abstract: Present invention presents a novel mechanism for reducing the amount of storage space necessary to perform error checking and correcting in a storage unit of a data processing machine by utilizing the information present in the parity checking portion of the storage unit.The novel mechanism is based on generating an error checking and correcting code which includes a first portion identifiable by parity bits normally stored with data words in a data storage device and a second portion. The second portion contains fewer bits than required in the prior art for an equivalent level of error checking and correcting and only the second portion is stored. When data is moved out of the storage device, the first portion is identified from the parity bits.

Abstract: An apparatus for enhancing the speed of access of an execution unit in a data processing machine to the high speed buffer memory array by storing data from the execution unit in the buffer before completing error checking operations.