Patents by Inventor Joseph A. Pryluck

Joseph A. Pryluck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: H607
    Abstract: An addressable delay memory device which operates as a dual mode device. In he first mode, the addressable delay memory functions as a first in-first out delay memory in which the data is delayed for a predetermined period. In the second mode, the addressable delay memory operates under the control of a remote controller and delays input data for three predetermined periods. The input data is sequentially stored in each of three sections of a dynamic random access memory means with the three delays being determined by the time required to fill each of the three sections. The delayed data from each of the three sections is coupled to a static random access memory means. The remote controller may request that the data words from any of the three groups of delayed data be placed on the output of the addressable delay memory device.
    Type: Grant
    Filed: June 27, 1986
    Date of Patent: March 7, 1989
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Joseph A. Pryluck