Patents by Inventor Joseph A. Schaefer

Joseph A. Schaefer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9927857
    Abstract: A process identifier for a job is collected. The job runs on a plurality of nodes. The job is identified using the process identifier. A node for the job is identified. An amount of power consumed by the node to run the job is determined.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: March 27, 2018
    Assignee: INTEL CORPORATION
    Inventors: Justin J. Song, Devadatta V. (Deva) Bodas, Muralidhar (Murali) Rajappa, Andy Hoffman, James W. (Jimbo) Alexander, Joseph A. Schaefer, Sunil K. Mahawar
  • Patent number: 9921633
    Abstract: An indication of a mode for a job is received. An available power for the job is determined based on the mode. A first power for the job is allocated based on the available power. A first frequency for the job is determined based on the available power. The first power is adjusted based on the available power.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: March 20, 2018
    Assignee: INTEL CORPORATION
    Inventors: Devadatta V. (Deva) Bodas, Justin J. Song, Muralidhar (Murali) Rajappa, Andy Hoffman, James W. (Jimbo) Alexander, Joseph A. Schaefer, Sunil K. Mahawar
  • Patent number: 9575536
    Abstract: A non-transitory computer readable storage medium having stored thereon instructions executable by one or more processors to perform operations including: receiving a plurality of input parameters including (i) a workload type, (ii) a list of selected nodes belonging to a distributed computer system, and (iii) a list of frequencies; responsive to receiving the plurality of workload parameters, retrieving calibration data from a calibration database; generating a power estimate based on the plurality of workload parameters and the calibration data; and providing the power estimate to a resource manager is shown. Alternatively, the input parameters may include (i) a workload type, (ii) a list of selected nodes belonging to a distributed computer system, and (iii) an amount of available power, wherein the estimator may provide an estimation of the frequency at which the nodes should operate to utilize as much of the available power without exceeding the available power.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: February 21, 2017
    Assignee: Intel Corporation
    Inventors: Muralidhar Rajappa, Andy Hoffman, Devadatta Bodas, Justin Song, James Alexander, Joseph A. Schaefer, Sunil Mahawar
  • Publication number: 20160054775
    Abstract: A non-transitory computer readable storage medium having stored thereon instructions executable by one or more processors to perform operations including: receiving a plurality of input parameters including (i) a workload type, (ii) a list of selected nodes belonging to a distributed computer system, and (iii) a list of frequencies; responsive to receiving the plurality of workload parameters, retrieving calibration data from a calibration database; generating a power estimate based on the plurality of workload parameters and the calibration data; and providing the power estimate to a resource manager is shown. Alternatively, the input parameters may include (i) a workload type, (ii) a list of selected nodes belonging to a distributed computer system, and (iii) an amount of available power, wherein the estimator may provide an estimation of the frequency at which the nodes should operate to utilize as much of the available power without exceeding the available power.
    Type: Application
    Filed: December 24, 2014
    Publication date: February 25, 2016
    Inventors: Muralidhar Rajappa, Andy Hoffman, Devadatta Bodas, Justin Song, James Alexander, Joseph A. Schaefer, Sunil Mahawar
  • Publication number: 20160054780
    Abstract: An indication of a mode for a job is received. An available power for the job is determined based on the mode. A first power for the job is allocated based on the available power. A first frequency for the job is determined based on the available power. The first power is adjusted based on the available power.
    Type: Application
    Filed: December 24, 2014
    Publication date: February 25, 2016
    Inventors: Devadatta V. (Deva) Bodas, Justin J. Song, Muralidhar (Murali) Rajappa, Andy Hoffman, James W. (Jimbo) Alexander, Joseph A. Schaefer, Sunil K. Mahawar
  • Publication number: 20160054774
    Abstract: A process identifier for a job is collected. The job runs on a plurality of nodes. The job is identified using the process identifier. A node for the job is identified. An amount of power consumed by the node to run the job is determined.
    Type: Application
    Filed: December 24, 2014
    Publication date: February 25, 2016
    Inventors: Justin J. Song, Devadatta V. (Deva) Bodas, Muralidhar (Murali) Rajappa, Andy Hoffman, James W. (Jimbo) Alexander, Joseph A. Schaefer, Sunil K. Mahawar
  • Publication number: 20160054779
    Abstract: A method of managing power and performance of a High-performance computing (HPC) systems, including: determining a power budget for a HPC system, wherein the HPC system includes a plurality of interconnected HPC nodes operable to execute a job, determining a power and cooling capacity of the HPC system, allocating the power budget to the job to maintain a power consumption of the HPC system within the power budget and the power and cooling capacity of the HPC system, and executing the job on selected HPC nodes is shown.
    Type: Application
    Filed: December 24, 2014
    Publication date: February 25, 2016
    Inventors: Devadatta BODAS, Muralidhar RAJAPPA, Justin SONG, Andy HOFFMAN, Joseph A. SCHAEFER, Sunil MAHAWAR
  • Patent number: 9104821
    Abstract: In some embodiments a detector detects a host or device coupled via a link. A port negotiates with a port of the detected host or device and determines whether to operate as a host and/or as a device. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: August 11, 2015
    Assignee: Intel Corporation
    Inventors: Robert A. Dunstan, Gary A. Solomon, Joseph A. Schaefer
  • Publication number: 20130246674
    Abstract: In some embodiments a Universal Serial Bus cable includes a first differential pair to transmit bus signals, and a second differential pair to transmit bus signals in a same direction as the bus signals transmitted by the first differential pair. In this manner, a bandwidth of the Universal Serial Bus cable is doubled in that same direction. Other embodiments are described and claimed.
    Type: Application
    Filed: December 21, 2012
    Publication date: September 19, 2013
    Inventors: Gary Solomon, Robert A. Dunstan, Joseph A. Schaefer, Brad Saunders
  • Publication number: 20100169511
    Abstract: In some embodiments a detector detects a host or device coupled via a link. A port negotiates with a port of the detected host or device and determines whether to operate as a host and/or as a device. Other embodiments are described and claimed.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Inventors: Robert A. Dunstan, Gary A. Solomon, Joseph A. Schaefer
  • Patent number: 7447208
    Abstract: A method for accessing a configuration space of a device is described. The method includes setting a first field of a packet to a value to specify a destination device, and setting a second field of the packet to a defined value to indicate that the packet is a configuration access packet. The method further includes setting a third field of the configuration access packet to a value to select one of a plurality of configuration apertures of a configuration space of the destination device, and setting a fourth field of the configuration access packet to a value to address a specific memory location within the selected aperture.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: November 4, 2008
    Assignee: Intel Corporation
    Inventors: David E. Mayhew, Todd R. Comins, Lynne M. Brocco, Joseph A. Schaefer, Gary A. Solomon, Edward Butler
  • Patent number: 7443869
    Abstract: A queuing mechanism is described for managing packets between agents of a computer system. The queuing mechanism includes an ordered queue including a plurality of queue registers to store a plurality of packets. The queuing mechanism also includes a bypass queue coupled to the ordered queue, wherein, if a packet at head of the ordered queue is a delayed request and is stalled for lack of flow control credit, then the stalled packet is moved into the bypass queue.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: October 28, 2008
    Assignee: Intel Corporation
    Inventors: Gary A. Solomon, Edward Butler, Joseph A. Schaefer, David E. Mayhew, Todd R. Comins, Lynne M. Brocco
  • Patent number: 7320080
    Abstract: A switching fabric handles transactions using a protocol that directs packets based on path routing information. Components participate in transactions using a protocol that issues packets based on physical location of a destination device over the switching fabric, by establishing a virtual link partner relationship between the components.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: January 15, 2008
    Assignee: Intel Corporation
    Inventors: Gary A. Solomon, Edward Butler, Joseph A. Schaefer
  • Patent number: 7167941
    Abstract: A method and an apparatus to configure a multi-port device are disclosed. The method includes defining a first set of pointers, one for each port of the multi-port device, and storing the first set of pointers in one or more capability structures of the multi-port device.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: January 23, 2007
    Assignee: Intel Corporation
    Inventors: Peter I. Iskiyan, Joseph A. Schaefer, Gary A. Solomon
  • Patent number: 6785806
    Abstract: A BIOS having a set of effectors to initialize harware within the system. The BIOS having a set of macros, each macro of the set of macros having a reference to an effector of the set of effectors, each macro of the set of macros having a set of arguments.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: August 31, 2004
    Assignee: Intel Corporation
    Inventors: Joseph A. Schaefer, Michael F. Kartoz, Robert L. Huff, Kimberly A. Davis, Kirk Brannock, Donald Hewett, Daniel A. Rich, William J. Chalmers
  • Patent number: 6732261
    Abstract: In one embodiment, the invention is a method. The method includes receiving expected values of a configuration. The method also includes comparing the expected values with values of a configuration database. Furthermore, the method includes reporting results of the comparing.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: May 4, 2004
    Assignee: Intel Corporation
    Inventors: William J. Chalmers, Joseph A. Schaefer, Kimberly A. Davis, Don G. Craven, Daniel A. Rich
  • Patent number: 6629192
    Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a BIOS embodied in a non-volatile storage device. The apparatus also includes a non-volatile storage manager embodied in the non-volatile storage device, the non-volatile storage manager controlling access to a portion of the BIOS.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: September 30, 2003
    Assignee: Intel Corporation
    Inventors: Joseph A. Schaefer, Dave Edwards, Kirk Brannock, William J. Chalmers
  • Publication number: 20030182545
    Abstract: In one embodiment, the invention is a method. The method includes receiving expected values of a configuration. The method also includes comparing the expected values with values of a configuration database. Furthermore, the method includes reporting results of the comparing.
    Type: Application
    Filed: December 30, 1999
    Publication date: September 25, 2003
    Inventors: WILLIAM J. CHALMERS, JOSEPH A. SCHAEFER, KIMBERLY A. DAVIS, DON G. CRAVEN, DANIEL A. RICH
  • Patent number: 6606679
    Abstract: Disclosed are a system and method of transmitting data in a processing platform. A switch may comprise an upstream port coupled to a root device to communicate with a processing system. The switch may also comprise a plurality of downstream ports where each downstream port is adapted to be coupled to a device. Data may be transmitted between downstream ports based upon routing information for transmitting data from the upstream port to each of the downstream ports.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: August 12, 2003
    Assignee: Intel Corporation
    Inventors: Gary A. Solomon, Joseph A. Schaefer
  • Patent number: 6594663
    Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a first d-node having a pointer to a subordinate d-node and an identifier. The apparatus also includes a set of d-nodes, each d-node of the set of d-nodes having an identifier, a pointer to a peer d-node, a pointer to a subordinate d-node and a pointer to an entry. The set of d-nodes is accessible through the pointer of the first d-node. The apparatus also includes a set of entries, each entry of the set of entries having an identifier, a type, a value, and a pointer to an entry. The value of each entry embodies data corresponding to a configuration of a system.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: July 15, 2003
    Assignee: Intel Corporation
    Inventors: Joseph A. Schaefer, Michael F. Kartoz, Robert L. Huff, Kimberly A. Davis, Kirk Brannock, Donald Hewett, William J. Chalmers