Abstract: An improved architecture for an EPROM PAL utilizing two bit lines is disclosed. The drains of the EPROM cells of a given column of an array are coupled together to a first bit line. The first line is coupled to a sensing circuit. The sources of the EPROM cells are coupled together to a second bit line which is then coupled through a current limiting transistor. The gate of the transistor is coupled to the first bit line to receive a feedback signal for controlling the current on the bit lines. The current limiting feature provides for shorter transition periods between "on" and "off" states which results in an improved speed performance of the device.

Abstract: A non-volatile memory and in particular the timing apparatus for generating sequence of signals needed for storing and recalling data is described. The memory cell employs an E.sup.2 cell which is coupled to a bistable (static) RAM cell. "State machine" logic is employed to obtain the proper sequence of signals needed for storing and recalling.