Patents by Inventor Joseph Abys

Joseph Abys has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10541140
    Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: January 21, 2020
    Assignee: MACDERMID ENTHONE INC.
    Inventors: Thomas B. Richardson, Joseph A. Abys, Wenbo Shao, Chen Wang, Vincent Paneccasio, Jr., Cai Wang, Xuan Lin, Theodore Antonellis
  • Patent number: 10221496
    Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: March 5, 2019
    Assignee: MacDermid Enthone Inc.
    Inventors: Thomas B. Richardson, Wenbo Shao, Xuan Lin, Cai Wang, Vincent Paneccasio, Jr., Joseph A. Abys, Yun Zhang, Richard Hurtubise, Chen Wang
  • Publication number: 20190003068
    Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.
    Type: Application
    Filed: May 24, 2011
    Publication date: January 3, 2019
    Applicant: ENTHONE INC.
    Inventors: Thomas B. Richardson, Wenbo Shao, Xuan Lin, Cai Wang, Vincent Paneccasio, JR., Joseph A. Abys, Yun Zhang, Richard Hurtubise, Chen Wang
  • Patent number: 10103029
    Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: October 16, 2018
    Assignee: MacDermid Enthone Inc.
    Inventors: Thomas B. Richardson, Joseph A. Abys, Wenbo Shao, Chen Wang, Vincent Paneccasio, Cai Wang, Sean Xuan Lin, Theodore Antonellis
  • Patent number: 10017863
    Abstract: A method and composition for enhancing corrosion resistance, wear resistance, and contact resistance of a substrate comprising a copper or copper alloy surface. The composition comprises a phosphorus oxide compound selected from the group consisting of a phosphonic acid, a phosphonate salt, a phosphonate ester, a phosphoric acid, a phosphate salt, a phosphate ester, and mixtures thereof; a nitrogen-containing organic compound selected from the group consisting of primary amine, secondary amine, tertiary amine, and aromatic heterocycle comprising nitrogen; and an alcohol.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: July 10, 2018
    Inventors: Joseph A. Abys, Shenliang Sun, Edward J. Kudrak, Katrin Zschintzsch, Theodore Antonellis
  • Patent number: 9730321
    Abstract: Compositions and methods for silver plating onto metal surfaces such as PWBs in electronics manufacture to produce a silver plating which is greater than 80 atomic % silver, tarnish resistant, and has good solderability.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: August 8, 2017
    Inventors: Yung-Herng Yau, Thomas B. Richardson, Joseph A. Abys, Karl F. Wengenroth, Anthony Fiore, Chen Xu, Chonglun Fan, John Fudala
  • Publication number: 20160254156
    Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.
    Type: Application
    Filed: May 6, 2016
    Publication date: September 1, 2016
    Inventors: Thomas B. Richardson, Joseph A. Abys, Wenbo Shao, Chen Wang, Vincent Paneccasio, Cai Wang, Xuan Lin, Theodore Antonellis
  • Publication number: 20160234947
    Abstract: Compositions and methods for enhancing adhesion between a copper conducting layer and a dielectric material during manufacture of a printed circuit board. Conditioning compositions contain a functional organic compound and preferably a transition metal ion. The functional organic compound, e.g., a purine derivative, is capable of forming a self-assembled monolayer. Adhesion promoting compositions contain an acid, preferably an inorganic acid, and an oxidant. The latter compositions may also contain a corrosion inhibitor and/or a transition metal ion selected from among Zn, Ni, Co, Cu, Ag, Au, Pd or another Pt group metal. The corrosion inhibitor may comprise a nitrogen-containing aromatic heterocyclic compound.
    Type: Application
    Filed: April 21, 2016
    Publication date: August 11, 2016
    Inventors: Abayomi I. Owei, Joseph A. Abys, Theodore Antonellis, Eric Walch
  • Patent number: 9338896
    Abstract: Compositions and methods for enhancing adhesion between a copper conducting layer and a dielectric material during manufacture of a printed circuit board. Conditioning compositions contain a functional organic compound and preferably a transition metal ion. The functional organic compound, e.g., a purine derivative, is capable of forming a self-assembled monolayer. Adhesion promoting compositions contain an acid, preferably an inorganic acid, and an oxidant. The latter compositions may also contain a corrosion inhibitor and/or a transition metal ion selected from among Zn, Ni, Co, Cu, Ag, Au, Pd or another Pt group metal. The corrosion inhibitor may comprise a nitrogen-containing aromatic heterocyclic compound.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: May 10, 2016
    Assignee: ENTHONE, INC.
    Inventors: Abayomi I. Owei, Joseph A. Abys, Theodore Antonellis, Eric Walch
  • Publication number: 20160032479
    Abstract: Electrolytic plating compositions and electrolytic plating processes for the co-deposition of silver or silver alloy with fluoropolymer nanoparticles are provided. The silver or silver alloy composite coating containing fluoropolymer nanoparticles has enhanced functional properties such as a reduced coefficient of friction. The electrolytic plating composition comprises: (a) a silver ion source comprising silver methane sulfonate (Ag-MSA); (b) a complexing agent comprising a compound comprising a nitrogen-containing heterocyclic ring; (c) a pre-mix dispersion comprising fluoropolymer nanoparticles particles having a mean particle size of from about 10 nm and about 500 nm and a surfactant; and (d) an auxiliary surfactant comprising a cationic fluorosurfactant, wherein the composition has a pH of from about 8 to about 14.
    Type: Application
    Filed: March 14, 2014
    Publication date: February 4, 2016
    Applicant: ENTHONE INC.
    Inventors: Jingye Li, Joseph A. Abys, Edward J. Kudrak, JR.
  • Patent number: 9217205
    Abstract: A method is provided for imparting corrosion resistance onto a surface of a substrate. The method comprises contacting the surface of the substrate with an electrolytic plating solution comprising (a) a source of deposition metal ions of a deposition metal selected from the group consisting of zinc, palladium, silver, nickel, copper, gold, platinum, rhodium, ruthenium, chrome, and alloys thereof, (b) a pre-mixed dispersion of non-metallic nano-particles, wherein the non-metallic particles have a pre-mix coating of surfactant molecules thereon; and applying an external source of electrons to the electrolytic plating solution to thereby electrolytically deposit a metal-based composite coating comprising the deposition metal and non-metallic nano-particles onto the surface.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: December 22, 2015
    Assignee: Enthone Inc.
    Inventors: Joseph A. Abys, Edward J. Kudrak, Jr., Jingye Li, Chen Xu, Chonglun Fan
  • Patent number: 9175400
    Abstract: A method is provided for depositing a whisker resistant tin-based coating layer on a surface of a copper substrate. The method is useful for preparing an article comprising a copper substrate having a surface; and a tin-based coating layer on the surface of the substrate, wherein the tin-based coating layer has a thickness between 0.5 micrometers and 1.5 micrometers and has a resistance to formation of copper-tin intermetallics, wherein said resistance to formation of copper-tin intermetallics is characterized in that, upon exposure of the article to at least seven heating and cooling cycles in which each cycle comprises subjecting the article to a temperature of at least 217° C. followed by cooling to a temperature between about 20° C. and about 28° C., there remains a region of the tin coating layer that is free of copper that is at least 0.25 micrometers thick.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: November 3, 2015
    Assignee: Enthone Inc.
    Inventors: Yung-Herng Yau, Xingping Wang, Cai Wang, Robert Farrell, Pingping Ye, Edward J. Kudrak, Jr., Karl F. Wengenroth, Joseph A. Abys
  • Publication number: 20150257264
    Abstract: Compositions and methods for silver plating onto metal surfaces such as PWBs in electronics manufacture to produce a silver plating which is greater than 80 atomic % silver, tarnish resistant, and has good solderability.
    Type: Application
    Filed: March 24, 2015
    Publication date: September 10, 2015
    Applicant: Enthone Inc.
    Inventors: Yung-Herng Yau, Thomas B. Richardson, Joseph A. Abys, Karl F. Wengenroth, Anthony Fiore, Chen Xu, Chonglun Fan, John Fudala
  • Patent number: 8986434
    Abstract: Compositions and methods for silver plating onto metal surfaces such as PWBs in electronics manufacture to produce a silver plating which is greater than 80 atomic % silver, tarnish resistant, and has good solderability.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: March 24, 2015
    Assignee: Enthone Inc.
    Inventors: Yung-Herng Yau, Thomas B. Richardson, Joseph A. Abys, Karl F. Wengenroth, Anthony Fiore, Chen Xu, Chonglun Fan, John Fudala
  • Patent number: 8906217
    Abstract: There is provided a method and composition for applying a wear resistant composite coating onto a metal surface of an electrical component. The method comprises contacting the metal surface with an electrolytic plating composition comprising (a) a source of tin ions and (b) non-metallic particles, and applying an external source of electrons to the electrolytic plating composition to thereby electrolytically deposit the composite coating onto the metal surface, wherein the composite coating comprises tin metal and the non-metallic particles.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: December 9, 2014
    Assignee: Enthone Inc.
    Inventors: Joseph A. Abys, Jingye Li, Edward J. Kudrak, Jr., Chen Xu
  • Patent number: 8741390
    Abstract: A method and composition for enhancing corrosion resistance, wear resistance, and contact resistance of a device comprising a copper or copper alloy substrate and at least one metal-based layer on a surface of the substrate. The composition comprises a phosphorus oxide compound selected from the group consisting of a phosphonic acid, a phosphonate salt, a phosphonate ester, a phosphoric acid, a phosphate salt, a phosphate ester, and mixtures thereof; an organic compound comprising a nitrogen-containing functional group; and a solvent having a surface tension less than about 50 dynes/cm as measured at 25° C.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: June 3, 2014
    Assignee: Enthone Inc.
    Inventors: Joseph A. Abys, Shenliang Sun, Chonglun Fan, Edward J. Kudrak, Jr., Cai Wang
  • Publication number: 20140120722
    Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.
    Type: Application
    Filed: January 26, 2012
    Publication date: May 1, 2014
    Applicant: ENTHONE INC.
    Inventors: Thomas B. Richardson, Joseph A. Abys, Wenbo Shao, Chen Wang, Vincent Paneccasio, JR., Cai Wang, Xuan Lin, Theodore Antonellis
  • Patent number: 8703243
    Abstract: A method is disclosed for enhancing the corrosion resistance of a surface of a copper or copper alloy substrate. The method comprises depositing a metallic surface layer comprising a precious metal on a surface of the copper or copper alloy substrate by immersion displacement plating and exposing the electronic device to an aqueous composition comprising a first organic molecule comprising at least one functional group that interacts with and protects precious metal surfaces and a second organic molecule comprising at least one functional group that interacts with and protects copper surfaces.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: April 22, 2014
    Assignee: Enthone Inc.
    Inventors: Joseph A. Abys, Shenliang Sun, Theodore Antonellis
  • Publication number: 20140030425
    Abstract: Compositions and methods for enhancing adhesion between a copper conducting layer and a dielectric material during manufacture of a printed circuit board. Conditioning compositions contain a functional organic compound and preferably a transition metal ion. The functional organic compound, e.g., a purine derivative, is capable of forming a self-assembled monolayer. Adhesion promoting compositions contain an acid, preferably an inorganic acid, and an oxidant. The latter compositions may also contain a corrosion inhibitor and/or a transition metal ion selected from among Zn, Ni, Co, Cu, Ag, Au, Pd or another Pt group metal. The corrosion inhibitor may comprise a nitrogen-containing aromatic heterocyclic compound.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 30, 2014
    Applicant: ENTHONE INC.
    Inventors: Abayomi I. OWEI, Joseph A. ABYS, Theodore ANTONELLIS, Eric WALCH
  • Publication number: 20130199935
    Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.
    Type: Application
    Filed: May 24, 2011
    Publication date: August 8, 2013
    Applicant: ENTHONE INC.
    Inventors: Thomas B. Richardson, Wenbo Shao, Xuan Lin, Cai Wang, Vincent Paneccasio, JR., Joseph A. Abys, Yun Zhang, Richard Hurtubise, Chen Wang