Patents by Inventor JOSEPH ANDRE GALLEGOS

JOSEPH ANDRE GALLEGOS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated capacitor with sidewall having reduced roughness
    Patent number: 11798979
    Abstract: An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: October 24, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Elizabeth Costner Stewart, Jeffrey A. West, Thomas D. Bonifield, Joseph Andre Gallegos, Jay Sung Chun, Zhiyi Yu
  • INTEGRATED CAPACITOR WITH SIDEWALL HAVING REDUCED ROUGHNESS
    Publication number: 20210143249
    Abstract: An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.
    Type: Application
    Filed: January 25, 2021
    Publication date: May 13, 2021
    Inventors: ELIZABETH COSTNER STEWART, JEFFREY A. WEST, THOMAS D. BONIFIELD, JOSEPH ANDRE GALLEGOS, JAY SUNG CHUN, ZHIYI YU
  • Integrated capacitor with sidewall having reduced roughness
    Patent number: 10978548
    Abstract: A method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion. The dielectric layer is etched, and a top plate is then formed on top of the dielectric feature.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: April 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Elizabeth Costner Stewart, Jeffrey A. West, Thomas D. Bonifield, Joseph Andre Gallegos, Jay Sung Chun, Zhiyi Yu
  • INTEGRATED CAPACITOR WITH SIDEWALL HAVING REDUCED ROUGHNESS
    Publication number: 20180130870
    Abstract: A method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion. The dielectric layer is etched, and a top plate is then formed on top of the dielectric feature.
    Type: Application
    Filed: November 10, 2016
    Publication date: May 10, 2018
    Inventors: ELIZABETH COSTNER STEWART, JEFFREY A. WEST, THOMAS D. BONIFIELD, JOSEPH ANDRE GALLEGOS, JAY SUNG CHUN, ZHIYI YU