Patents by Inventor Joseph Andrew Iadanza
Joseph Andrew Iadanza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8793365Abstract: A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms.Type: GrantFiled: March 4, 2009Date of Patent: July 29, 2014Assignee: International Business Machines CorporationInventors: Igor Arsovski, Anthony Richard Bonaccio, Hayden C. Cranford, Jr., Alfred Degbotse, Joseph Andrew Iadanza, Todd Edwin Leonard, Pradeep Thiagarajan, Sebastian Theodore Ventrone
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Publication number: 20100228861Abstract: A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms.Type: ApplicationFiled: March 4, 2009Publication date: September 9, 2010Applicant: International Business Machines CorporationInventors: Igor Arsovski, Anthony Richard Bonaccio, Hayden C. Cranford, JR., Alfred Degbotse, Joseph Andrew Iadanza, Todd Edwin Leonard, Pradeep Thiagarajan, Sebastian Theodore Ventrone
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Patent number: 7545297Abstract: A digital to analog converter. The digital to analog converter including a current mirror comprising N stages, each stage comprising 2n?1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N?1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.Type: GrantFiled: August 29, 2007Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Wagdi William Abadeer, Anthony Richard Bonaccio, Joseph Andrew Iadanza
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Patent number: 7545298Abstract: A design structure embodied in a machine readable medium, the design structure including a current mirror including N stages, each stage comprising 2n?1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N?1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.Type: GrantFiled: March 10, 2008Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Wagdi William Abadeer, Anthony Richard Bonaccio, Joseph Andrew Iadanza
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Publication number: 20090058704Abstract: A design structure embodied in a machine readable medium, the design structure including a current mirror including N stages, each stage comprising 2n-1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N?1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.Type: ApplicationFiled: March 10, 2008Publication date: March 5, 2009Inventors: Wagdi William Abadeer, Anthony Richard Bonaccio, Joseph Andrew Iadanza
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Publication number: 20090058703Abstract: A digital to analog converter. The digital to analog converter including a current mirror comprising N stages, each stage comprising 2n?1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N?1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.Type: ApplicationFiled: August 29, 2007Publication date: March 5, 2009Inventors: Wagdi William Abadeer, Anthony Richard Bonaccio, Joseph Andrew Iadanza
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Patent number: 6717997Abstract: In an electronic system such as a communications integrated circuit including a plurality of components, e.g., transmitters, each of which are operative to demand current responsive to a control signal applied thereto, an apparatus for time-distributing current demand comprises a first phase control circuit configured to receive a reference clock signal and operative to generate a synchronized output signal therefrom, the first phase control circuit generating a phase control signal for synchronizing the output signal to the reference clock signal. A plurality of second phase control circuits is responsive to at least one input control signal and to the phase control signal and operative to apply a plurality of phased output control signals to the plurality of components, the phased output control signals phased with respect to one another by time intervals that are dependent upon the phase control signal.Type: GrantFiled: December 1, 1998Date of Patent: April 6, 2004Assignee: International Business Machines CorporationInventors: Hayden Clavie Cranford, Jr., Joseph Andrew Iadanza
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Patent number: 6233191Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: February 22, 2000Date of Patent: May 15, 2001Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III
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Patent number: 6130854Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: October 10, 2000Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Terrance John Zittritsch
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Patent number: 6118707Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 10, 1998Date of Patent: September 12, 2000Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Terrance John Zittritsch
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Patent number: 6091645Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: July 18, 2000Assignee: International Business Machines CorporationInventor: Joseph Andrew Iadanza
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Patent number: 6075745Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: June 13, 2000Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 6044031Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: March 28, 2000Assignee: International Business Machines CorporationInventors: Joseph Andrew Iadanza, Frank Ray Keyser, III
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Patent number: 6038192Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 10, 1998Date of Patent: March 14, 2000Assignee: International Business Machines CorporationInventors: Kim P. N. Clinton, Joseph Andrew Iadanza, Frank Ray Keyser, III, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 6023421Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: February 8, 2000Assignee: International Business Machines CorporationInventors: Kim P. N. Clinton, Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 5949719Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: September 7, 1999Assignee: International Business Machines CorporationInventors: Kim P. N. Clinton, Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 5914906Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: December 20, 1995Date of Patent: June 22, 1999Assignee: International Business Machines CorporationInventors: Joseph Andrew Iadanza, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 5815009Abstract: A process tolerant delay circuit includes a plurality of inverters that receive an input signal and provide an output signal related to the input signal but including a propagation delay of the plurality of inverters. At least one inverter comprises FETs of minimum channel lengths dependent upon a fabrication process by which the circuit was made. Accordingly, the plurality of inverters have a propagation delay dependent upon the fabrication process. A delay compensation device receives the output signal of the inverters and provides a compensated output signal related to the received signal but including a variable delay established in accordance with a control signal. A process sense stack provides the control signal only during a transition of the input signal, and with a value dependent upon a channel length of a FET device thereof.Type: GrantFiled: December 30, 1996Date of Patent: September 29, 1998Assignee: International Business Machines CorporationInventors: Joseph Andrew Iadanza, Makoto Ueda
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Patent number: 5802003Abstract: A system is provided for providing functional, initialization and reset access to a plurality of memory cells of a memory array, using a single cell write port and a single cell read port. In addition to functional address and data buses, initialization address and data buses are provided. The invention is disclosed in association with a field-programmable memory array having multiple sub-arrays therein. The address units for each sub-array are provided to programmably provide address information to the wordlines of each sub-array from an initialization address bus or a functional address bus. Similarly, readhead and writehead circuits within each sub-array are also programmable to propagate data between initialization or functional data buses and the memory cells of the sub-array. The address units, readheads, and writeheads are all responsive to a dominant reset signal to reset the associated cells.Type: GrantFiled: December 20, 1995Date of Patent: September 1, 1998Assignee: International Business Machines CorporationInventors: Joseph Andrew Iadanza, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie
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Patent number: 5781032Abstract: A programmable logic cell has four cell input nodes and a plurality of combinational logic circuits. Four inverter circuits are provided for programmably inverting respective input logic signals, each inverter circuit having an inverter input node connected to a respective cell input node for accepting its respective input logic signal therefrom. Each inverter is programmable into a first state wherein a logic signal representing the complement of the input logic signal is provided to the inverter output node, and a second state wherein a logic signal representing the non-complement of the input logic signal is provided to the inverter output node. The inverter circuits buffer their input logic signals in both their first and second states.Type: GrantFiled: September 9, 1996Date of Patent: July 14, 1998Assignee: International Business Machines CorporationInventors: Allan Robert Bertolet, Kim P.N. Clinton, Christine Marie Fuller, Scott Whitney Gould, Steven Paul Hartman, Joseph Andrew Iadanza, Frank Ray Keyser, Eric Ernest Millham, Timothy Shawn Reny, Brian A. Worth, Gulson Yasar, Terrance John Zittritsch