Patents by Inventor Joseph Andrew Martin

Joseph Andrew Martin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7504712
    Abstract: An electronic device comprises a leadframe attached to a die and embedded in a mold packaging with enhanced adhesion property. The leadframe comprises a bonding surface, a soldering surface, a mold adhesion surface, and a die attachment surface wherein the soldering surface and bonding surface are selectively plated with nickel/palladium/gold. The mold adhesion surface and the die attachment surface are roughened for better attachment to a mold and a die respectively.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: March 17, 2009
    Assignee: QPL Limited
    Inventors: Joseph Andrew Martin, King Yin Fred Fu, Hoi Ping Patrick Phen
  • Patent number: 6818472
    Abstract: An integrated circuit package including a substrate having opposing first and second surfaces. The substrate has conductive traces disposed therein. A semiconductor die is mounted on the first surface of the substrate and a silicon heat sink disposed on a portion of the semiconductor die. A plurality of wire bonds connect the semiconductor die to the conductive traces of the substrate and an overmold material covers the first surface of the substrate and a remainder of the semiconductor die. A ball grid array is disposed on the second surface of the substrate. Bumps of the ball grid array are in electrical connection with the conductive traces.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: November 16, 2004
    Assignee: Asat Ltd.
    Inventors: Chun Ho Fan, Joseph Andrew Martin, Ming Wang Sze, Tak Sang Yeung
  • Patent number: 6800948
    Abstract: An integrated circuit package including a substrate having opposing first and second surfaces. The substrate has conductive traces disposed therein. A semiconductor die is mounted on the first surface of the substrate and a silicon heat sink disposed on a portion of the semiconductor die. A plurality of wire bonds connect the semiconductor die to the conductive traces of the substrate and an overmold material covers the first surface of the substrate and a remainder of the semiconductor die. A ball grid array is disposed on the second surface of the substrate. Bumps of the ball grid array are in electrical connection with the conductive traces.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: October 5, 2004
    Assignee: ASAT Ltd.
    Inventors: Chun Ho Fan, Joseph Andrew Martin, Ming Wang Sze, Tak Sang Yeung