Abstract: In a fail soft synchronization clock system having a plurality of central processing units and a plurality of input-output units operably connected to one or more remotely located volatile cache memories there is provided a free-running, non-synchronized clock in each central processing unit. The clock outputs are connected to sets of synchronizing clock system logic circuits, one for each central processing unit, which disable the clocks of all other central processing units and selects their own associated clock as the input for producing a plurality of synchronized outputs employed in turn to time the operation of the processing system which is operably connected to the cache memories.