Abstract: A system comprising a network-on-chip (NOC) fabric comprising a plurality of routes to communicate data between a plurality of agents; a plurality of built-in self-test (BIST) generators, wherein a BIST generator of the plurality of BIST generators is coupled between an agent of the plurality of agents and the NOC fabric and is to transmit at least one test pattern through the NOC fabric; and a plurality of BIST checkers, wherein a BIST checker of the plurality of BIST checkers is coupled between the agent of the plurality of agents and the NOC fabric and is to receive at least one test pattern through the NOC fabric from at least one of the plurality of BIST generators and to verify whether the at least one test pattern was transmitted correctly through the NOC fabric.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: A re-fetching cache memory improves efficiency of a system, for example by advantageously sharing the cache memory and/or by increasing performance. When some or all of the cache memory is temporarily used for another purpose, some or all of a data portion of the cache memory is flushed, and some or all of a tag portion is saved in an archive. In some embodiments, some or all of the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. When the temporary use completes, optionally and/or selectively, at least some of the tag portion is repopulated from the archive, and the data portion is re-fetched according to the repopulated tag portion. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.

Abstract: A re-fetching cache memory improves efficiency of a processor, for example by reducing power consumption and/or by advantageously sharing the cache memory. When the cache memory is disabled or temporarily used for another purpose, a data portion of the cache memory is flushed, and some or all of a tag portion is saved in an archive. In some embodiments, the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. When the cache memory is re-enabled or when the temporary use completes, optionally and/or selectively, the tag portion is repopulated from some or all of the archive, and the data portion is re-fetched according to the repopulated tag portion. The re-fetching is optionally performed in a cache coherent fashion. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.

Abstract: A system for managing data in multiple data processing devices using common data paths. Embodiments of the invention comprise a first data processing system comprising a cacheable coherent memory space; and a second data processing system communicatively coupled to the first data processing system with the second data processing system comprising at least one bridge, wherein the bridge is operable to perform an uncacheable remote access to the cacheable coherent memory space of the first data processing system. In some embodiments, the access performed by the bridge comprises a data write to the memory of the first data processing system for incorporation into the cacheable coherent memory space of the first data system. In other embodiments, the access performed by the bridge comprises a data read from the cacheable coherent memory space of the first data system.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: A reduced-power memory (such as for a cache memory system of a processor or a microprocessor) provides per-sector power/ground control and early address to advantageously reduce power consumption. Selective power control of sectors comprised in the reduced-power memory is responsive to a subset of address bits used to access the memory. The selective power control individually powers-up a selected one of the sectors in response to an access, and then powers-down the selected sector when the access is complete. The power-up is via an increase of differential between power and ground levels from a retention differential to an access differential. Time needed to vary the differential is masked by providing address information used by the selective power control in advance of providing other address information. For example, in a cache, a tag access is overlapped with power-up of a selected sector, thus masking latency of powering up the selected sector.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: A re-fetching cache memory improves efficiency of a processor, for example by reducing power consumption and/or increasing performance. When the cache memory is disabled or temporarily used for another purpose, a data portion of the cache memory is flushed, and a tag portion is saved in an archive. In some embodiments, the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. In some embodiments, less than the full tag portion is archived. When the cache memory is re-enabled or when the temporary use completes, optionally and/or selectively, the tag portion is repopulated from the archive, and the data portion is re-fetched according to the repopulated tag portion. In some embodiments, less than the full archive is restored. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.

Abstract: In accordance with the present invention a system for detecting transaction errors in a system comprising a plurality of data processing devices using a common system interconnect bus, comprises a node controller operably connected to said system interconnect bus and a plurality of interface agents communicatively coupled to said node controller. Error corresponding to transactions between said interface agents and other processing modules in said system are directed to said node controller; and wherein transaction errors that would not normally be communicated to said system interconnect bus are communicated by said node controller to said system interconnect bus to be available for detection. In an embodiment of the present invention, the interface agents operate in accordance with the hypertransport protocol. A system control and debug unit and a trace cache operably connected to the system bus can be used to diagnose and store errors conditions.

Abstract: A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain coherency on the interconnect on behalf of other nodes. In one embodiment, the interconnect does not permit retry of a transaction initiated thereon, and the memory bridge is configured to provide a response during a response phase of the transaction based on a state of a coherency block accessed by the transaction in the other nodes. In another embodiment, the node further comprises a plurality of interface circuits and a switch. Each of the plurality of interface circuits is configured to couple to an interface to receive coherency commands from other nodes. The switch is configured to selectively couple the plurality of interface circuits to the memory bridge to transmit the coherency commands to the memory bridge.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: A reduced-power memory (such as for a cache memory system of a processor or a microprocessor) provides per-sector ground control to advantageously reduce power consumption. Selective power control of a plurality of sectors comprised in the reduced-power memory is responsive to a subset of address bits for accessing the memory. The selective power control individually powers-up a selected one of the sectors in response to an access, and then powers-down the selected sector when the access is complete. The power-up is via a decrease in ground potential from a retention level to an access level. Time needed to vary the ground potential is optionally masked by providing address information used by the selective power control in advance of providing other address information. For example, in a cache, a tag access is overlapped with power-up of a selected sector, thus masking latency of powering up the selected sector.

Abstract: An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: A node includes a processor coupled to an interconnect and a memory bridge coupled to the interconnect. The processor is configured to maintain a first indication of whether or not a modification of data at a first address has been detected by the processor after a most recent load-linked (LL) instruction was executed by the processor to the first address. The memory bridge is responsible for internode coherency within the node, and is configured to initiate a first transaction on the interconnect in response to receiving a probe command from another node. The processor is configured, during a time period in which the processor has a second transaction outstanding to the first address, to change the first indication to the first state responsive to the first transaction.

Abstract: A node comprises one or more resources and a register programmable with an indication during use. The one or more resources are addressed with addresses within a local region of an address space. The indication identifies a second region of the address space that is aliased to the local region, and other nodes address the one or more resources using addresses in the second region.

Abstract: A system for servicing packet data transactions and input/output transactions includes an input port, an output port, a node controller, a packet manager, and a switching module. The input port is receives communications from a communicatively coupled processing device that include packet data transactions and input/output transactions. The output port transmits communications to a communicatively coupled processing device that include packet data transactions and input/output transactions. The node controller communicatively couples to a system bus of the processing device and services input/output transactions. The packet manager communicatively couples to the system bus of the processing device and services packet data transactions. A switching module communicatively couples to the input port, the output port, the node controller, and the packet manager and services the exchange of transaction cells among the input port, the output port, the node controller, and the packet manager.

Abstract: An apparatus comprises a first plurality of buffers configured to store operations belonging to a first virtual channel and a control circuit coupled to the first plurality of buffers. The first virtual channel includes first operations and second operations, wherein each of the first operations depend on at least one of the second operations during use. A first number of the first operations is less than or equal to a maximum. It is ambiguous, for a first received operation in the first virtual channel, whether the first received operation is one of the first operations or the second operations. A total number of the first plurality of buffers exceeds the maximum.

Abstract: A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain coherency on the interconnect on behalf of other nodes. In one embodiment, the interconnect does not permit retry of a transaction initiated thereon, and the memory bridge is configured to provide a response during a response phase of the transaction based on a state of a coherency block accessed by the transaction in the other nodes. In another embodiment, the node further comprises a plurality of interface circuits and a switch. Each of the plurality of interface circuits is configured to couple to an interface to receive coherency commands from other nodes. The switch is configured to selectively couple the plurality of interface circuits to the memory bridge to transmit the coherency commands to the memory bridge.