Abstract: Systems and methods for processing priority-based application threads on a realtime component are described. A mixing component submits blank buffers to the realtime component. The mixing component receives application thread data according to a priority-based schedule and writes the data using a second real-time thread to the buffers before the buffers into which the data is written are processed. Buffers are created on memory page boundaries with an offset into the memory page such that the least significant bits of a virtual memory address referencing the memory page can be used as an index into a circular buffer queue to determine which buffer is currently being processed. When writing into a buffer, a buffer that is a predetermined range of buffers behind the buffer currently being processed is used.

Abstract: Video frame buffers are controlled using a sequence of new-frame-indicators (e.g., FLIP) and no-new-frame-indicators (e.g., NOFLIP) in a frame indicator queue that is accessed with each display refresh. Video samples are loaded into a chain of video frame buffers that is “rotated” during the vertical blanking signal of the display to swap an old frame buffer out for a new frame buffer. The rotations of the frame buffer chain are controlled based on the frame indicators in the frame indicator queue to present new video samples to the display in a regular pattern, thereby providing smooth video playback.

Abstract: A system and method for adaptive estimation and compensation of clock drift in echo cancellers is provided. The invention includes an acoustic echo cancellation system with a built in adaptive clock drift compensation system. The acoustic echo cancellation system has an AEC component that performs acoustic echo cancellation on data from a capture buffer, by also using information derived from a render buffer. The clock drift compensation system has access to this capture buffer and render buffer. The clock drift compensation system includes a clock drift compensator that calculates, based on the current location of the capture data being processed by the AEC component as well as additional information, the ideal location in the render buffer from which the AEC component should process data. The clock drift compensator further adjusts the current location in the render buffer from which the AEC component processes data based, at least in part, upon this ideal location.

Abstract: Methods and computer-executable components for real-time scheduling of CPU resources are disclosed. A performance counter determines when to allocate CPU resources to a thread. When it is time to allocate the CPU resources, the performance counter issues a maskable or non-maskable interrupt to an advanced programmable interrupt controller (APIC). The APIC then issues a maskable non-maskable interrupt to the CPU. In response to receiving the non-maskable interrupt, the CPU allocates resources to the thread. In addition, the disclosed methods and computer-executable components also: (a) allow scheduling of CPU resources such that real-time threads are guaranteed respective portions of time slots, (b) enable real-time scheduling on a non-real-time operating system, and (c) provide scheduling of CPU resources on a uni-processor machine such that at least first and second real-time threads dependent on one another are synchronized.

Abstract: Methods and computer-executable components for real-time scheduling of CPU resources are disclosed. A performance counter determines when to allocate CPU resources to a thread. When it is time to allocate the CPU resources, the performance counter issues a maskable or non-maskable interrupt to an advanced programmable interrupt controller (APIC). The APIC then issues a maskable non-maskable interrupt to the CPU. In response to receiving the non-maskable interrupt, the CPU allocates resources to the thread. In addition, the disclosed methods and computer-executable components also: (a) allow scheduling of CPU resources such that real-time threads are guaranteed respective portions of time slots, (b) enable real-time scheduling on a non-real-time operating system, and (c) provide scheduling of CPU resources on a uni-processor machine such that at least first and second real-time threads dependent on one another are synchronized.

Abstract: The present invention is directed to a method and system for minimizing memory access latency during realtime processing. The method includes a mechanism for marking information that will be accessed during realtime processing. The marked information may include code, data, heaps, stacks, as well as other information. The method includes support for locking down all of the marked information so that it is present in a computing machine's physical memory so that no page faults will be incurred during realtime processing. The method additionally enables realtime processing code to allocate and free memory in a non-blocking manner. It does so by enabling the creation of heaps for use during realtime processing, wherein each heap supports allocating and freeing memory in a non-blocking fashion. Each heap tracks freed memory blocks using individual non-blocking tracking lists for each memory block size supported by that heap.

Abstract: Systems and methods to render tear free video in a multitasking operating environment are described. In one aspect, a video playback window portion of a desktop display is divided into non-overlapping first and second partitions. As video data is scanned into display memory which maps to the first and second partitions, current scan line input positions are monitored. Responsive to determining that the current scan line position is located in display memory associated with the second partition, display memory mapped to the second partition is not rendered and display memory mapped to the first partition is rendered into the video playback window.

Abstract: Methods and computer-executable components for real-time scheduling of CPU resources are disclosed. A performance counter determines when to allocate CPU resources to a thread. When it is time to allocate the CPU resources, the performance counter issues a maskable or non-maskable interrupt to an advanced programmable interrupt controller (APIC). The APIC then issues a maskable non-maskable interrupt to the CPU. In response to receiving the non-maskable interrupt, the CPU allocates resources to the thread. In addition, the disclosed methods and computer-executable components also: (a) allow scheduling of CPU resources such that real-time threads are guaranteed respective portions of time slots, (b) enable real-time scheduling on a non-real-time operating system, and (c) provide scheduling of CPU resources on a uni-processor machine such that at least first and second real-time threads dependent on one another are synchronized.